| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | vec_cmp.ll | 14 %sext = sext <2 x i1> %cmp to <2 x i8>
15 ret <2 x i8> %sext
23 %sext = sext <4 x i1> %cmp to <4 x i8>
24 ret <4 x i8> %sext
32 %sext = sext <8 x i1> %cmp to <8 x i8>
33 ret <8 x i8> %sext
43 %sext = sext <16 x i1> %cmp to <16 x i8>
44 ret <16 x i8> %sext
52 %sext = sext <16 x i1> %cmp to <16 x i8>
53 ret <16 x i8> %sext
[all …]
|
| D | vec_int_ext.ll | 18 %conv = sext i8 %vecext to i32
21 %conv2 = sext i8 %vecext1 to i32
24 %conv5 = sext i8 %vecext4 to i32
27 %conv8 = sext i8 %vecext7 to i32
45 %conv = sext i8 %vecext to i64
48 %conv2 = sext i8 %vecext1 to i64
66 %conv = sext i16 %vecext to i32
69 %conv2 = sext i16 %vecext1 to i32
72 %conv5 = sext i16 %vecext4 to i32
75 %conv8 = sext i16 %vecext7 to i32
[all …]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | vec_cmp.ll | 14 %sext = sext <2 x i1> %cmp to <2 x i8>
15 ret <2 x i8> %sext
23 %sext = sext <4 x i1> %cmp to <4 x i8>
24 ret <4 x i8> %sext
32 %sext = sext <8 x i1> %cmp to <8 x i8>
33 ret <8 x i8> %sext
43 %sext = sext <16 x i1> %cmp to <16 x i8>
44 ret <16 x i8> %sext
52 %sext = sext <16 x i1> %cmp to <16 x i8>
53 ret <16 x i8> %sext
[all …]
|
| /external/llvm/test/CodeGen/X86/ |
| D | setcc-combine.ll | 10 %sext = sext <4 x i1> %cmp to <4 x i32>
11 %cmp1 = icmp eq <4 x i32> %sext, zeroinitializer
13 %1 = sext i1 %0 to i32
24 %sext = sext <4 x i1> %cmp to <4 x i32>
25 %cmp1 = icmp ne <4 x i32> %sext, zeroinitializer
27 %1 = sext i1 %0 to i32
37 %sext = sext <4 x i1> %cmp to <4 x i32>
38 %cmp1 = icmp sle <4 x i32> %sext, zeroinitializer
40 %1 = sext i1 %0 to i32
51 %sext = sext <4 x i1> %cmp to <4 x i32>
[all …]
|
| D | pmovsx-inreg.ll | 10 %sext = sext <2 x i8> %wide.load35 to <2 x i64>
12 store <2 x i64> %sext, <2 x i64>* %out, align 8
27 %sext = sext <4 x i8> %wide.load35 to <4 x i64>
29 store <4 x i64> %sext, <4 x i64>* %out, align 8
38 %sext = sext <4 x i8> %wide.load35 to <4 x i32>
40 store <4 x i32> %sext, <4 x i32>* %out, align 8
55 %sext = sext <8 x i8> %wide.load35 to <8 x i32>
57 store <8 x i32> %sext, <8 x i32>* %out, align 8
66 %sext = sext <8 x i8> %wide.load35 to <8 x i16>
68 store <8 x i16> %sext, <8 x i16>* %out, align 8
[all …]
|
| /external/swiftshader/third_party/subzero/crosstest/ |
| D | test_icmp_i1vec.ll | 6 %cmp.sext = sext <16 x i1> %cmp to <16 x i8>
7 ret <16 x i8> %cmp.sext
15 %cmp.sext = sext <16 x i1> %cmp to <16 x i8>
16 ret <16 x i8> %cmp.sext
24 %cmp.sext = sext <16 x i1> %cmp to <16 x i8>
25 ret <16 x i8> %cmp.sext
33 %cmp.sext = sext <16 x i1> %cmp to <16 x i8>
34 ret <16 x i8> %cmp.sext
42 %cmp.sext = sext <16 x i1> %cmp to <16 x i8>
43 ret <16 x i8> %cmp.sext
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | setcc-combine.ll | 14 %sext = sext <4 x i1> %cmp to <4 x i32>
15 %cmp1 = icmp eq <4 x i32> %sext, zeroinitializer
17 %t1 = sext i1 %t0 to i32
29 %sext = sext <4 x i1> %cmp to <4 x i32>
30 %cmp1 = icmp ne <4 x i32> %sext, zeroinitializer
32 %t1 = sext i1 %t0 to i32
42 %sext = sext <4 x i1> %cmp to <4 x i32>
43 %cmp1 = icmp sle <4 x i32> %sext, zeroinitializer
45 %t1 = sext i1 %t0 to i32
59 %sext = sext <4 x i1> %cmp to <4 x i32>
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/BasicAA/ |
| D | q.bad.ll | 8 %sext.1 = sext i8 255 to i16
9 %sext.zext.1 = zext i16 %sext.1 to i64
10 %sext.2 = sext i8 255 to i32
11 %sext.zext.2 = zext i32 %sext.2 to i64
12 %a = getelementptr inbounds i8, i8* %mem, i64 %sext.zext.1
13 %b = getelementptr inbounds i8, i8* %mem, i64 %sext.zext.2
19 ; %a and %b only PartialAlias as, although they're both zext(sext(%num)) they'll extend the sign by…
22 %sext.1 = sext i8 %num to i16
23 %sext.zext.1 = zext i16 %sext.1 to i64
24 %sext.2 = sext i8 %num to i32
[all …]
|
| /external/llvm/test/Analysis/BasicAA/ |
| D | q.bad.ll | 8 %sext.1 = sext i8 255 to i16
9 %sext.zext.1 = zext i16 %sext.1 to i64
10 %sext.2 = sext i8 255 to i32
11 %sext.zext.2 = zext i32 %sext.2 to i64
12 %a = getelementptr inbounds i8, i8* %mem, i64 %sext.zext.1
13 %b = getelementptr inbounds i8, i8* %mem, i64 %sext.zext.2
19 ; %a and %b only PartialAlias as, although they're both zext(sext(%num)) they'll extend the sign by…
22 %sext.1 = sext i8 %num to i16
23 %sext.zext.1 = zext i16 %sext.1 to i64
24 %sext.2 = sext i8 %num to i32
[all …]
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.amdgcn.class.ll | 19 %sext = sext i1 %result to i32
20 store i32 %sext, i32 addrspace(1)* %out, align 4
35 %sext = sext i1 %result to i32
36 store i32 %sext, i32 addrspace(1)* %out, align 4
51 %sext = sext i1 %result to i32
52 store i32 %sext, i32 addrspace(1)* %out, align 4
68 %sext = sext i1 %result to i32
69 store i32 %sext, i32 addrspace(1)* %out, align 4
81 %sext = sext i1 %result to i32
82 store i32 %sext, i32 addrspace(1)* %out, align 4
[all …]
|
| /external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/ |
| D | sext.ll | 11 %s = sext i32 %t to i64
20 %s = sext i32 %t to i64
29 %s = sext i32 %t to i64
38 %s = sext i32 %t to i64
47 %s = sext i32 %t to i64
56 %s = sext i32 %t to i64
65 %s = sext i32 %u to i64
75 %n = sext i16 %s to i32
88 %t2 = sext i16 %t to i32
109 %b = sext i8 %a to i32
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.amdgcn.class.ll | 19 %sext = sext i1 %result to i32
20 store i32 %sext, i32 addrspace(1)* %out, align 4
35 %sext = sext i1 %result to i32
36 store i32 %sext, i32 addrspace(1)* %out, align 4
51 %sext = sext i1 %result to i32
52 store i32 %sext, i32 addrspace(1)* %out, align 4
68 %sext = sext i1 %result to i32
69 store i32 %sext, i32 addrspace(1)* %out, align 4
81 %sext = sext i1 %result to i32
82 store i32 %sext, i32 addrspace(1)* %out, align 4
[all …]
|
| D | fcmp.f16.ll | 22 %r.val.sext = sext i1 %r.val to i32
23 store i32 %r.val.sext, i32 addrspace(1)* %r
50 %r.val.sext = sext i1 %r.val to i32
51 store i32 %r.val.sext, i32 addrspace(1)* %r
73 %r.val.sext = sext i1 %r.val to i32
74 store i32 %r.val.sext, i32 addrspace(1)* %r
96 %r.val.sext = sext i1 %r.val to i32
97 store i32 %r.val.sext, i32 addrspace(1)* %r
119 %r.val.sext = sext i1 %r.val to i32
120 store i32 %r.val.sext, i32 addrspace(1)* %r
[all …]
|
| D | llvm.amdgcn.class.f16.ll | 21 %r.val.sext = sext i1 %r.val to i32
22 store i32 %r.val.sext, i32 addrspace(1)* %r
43 %r.val.sext = sext i1 %r.val to i32
44 store i32 %r.val.sext, i32 addrspace(1)* %r
65 %r.val.sext = sext i1 %r.val to i32
66 store i32 %r.val.sext, i32 addrspace(1)* %r
88 %r.val.sext = sext i1 %r.val to i32
89 store i32 %r.val.sext, i32 addrspace(1)* %r
104 %r.val.sext = sext i1 %r.val to i32
105 store i32 %r.val.sext, i32 addrspace(1)* %r
[all …]
|
| /external/llvm/test/Transforms/InstCombine/ |
| D | sext.ll | 11 %s = sext i32 %t to i64
20 %s = sext i32 %t to i64
29 %s = sext i32 %t to i64
38 %s = sext i32 %t to i64
47 %s = sext i32 %t to i64
56 %s = sext i32 %t to i64
65 %s = sext i32 %u to i64
75 %n = sext i16 %s to i32
88 %t2 = sext i16 %t to i32
109 %b = sext i8 %a to i32
[all …]
|
| /external/llvm/test/Analysis/ScalarEvolution/ |
| D | infer-prestart-no-wrap.ll | 3 define void @infer.sext.0(i1* %c, i32 %start, i32* %buf) {
4 ; CHECK-LABEL: Classifying expressions for: @infer.sext.0
12 %idx.inc.sext = sext i32 %idx.inc to i64
13 ; CHECK: %idx.inc.sext = sext i32 %idx.inc to i64
14 ; CHECK-NEXT: --> {(1 + (sext i32 %start to i64))<nsw>,+,1}<nsw><%loop>
36 %idx.inc.sext = zext i32 %idx.inc to i64
37 ; CHECK: %idx.inc.sext = zext i32 %idx.inc to i64
51 define void @infer.sext.1(i32 %start, i1* %c) {
52 ; CHECK-LABEL: Classifying expressions for: @infer.sext.1
60 %idx.sext = sext i32 %idx to i64
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/ScalarEvolution/ |
| D | infer-prestart-no-wrap.ll | 3 define void @infer.sext.0(i1* %c, i32 %start, i32* %buf) {
4 ; CHECK-LABEL: Classifying expressions for: @infer.sext.0
12 %idx.inc.sext = sext i32 %idx.inc to i64
13 ; CHECK: %idx.inc.sext = sext i32 %idx.inc to i64
14 ; CHECK-NEXT: --> {(1 + (sext i32 %start to i64))<nsw>,+,1}<nsw><%loop>
36 %idx.inc.sext = zext i32 %idx.inc to i64
37 ; CHECK: %idx.inc.sext = zext i32 %idx.inc to i64
51 define void @infer.sext.1(i32 %start, i1* %c) {
52 ; CHECK-LABEL: Classifying expressions for: @infer.sext.1
60 %idx.sext = sext i32 %idx to i64
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/Delinearization/ |
| D | himeno_2.ll | 29 …sext i32 %a.deps to i64) * (1 + (sext i32 %a.cols to i64))) + %a.base),+,(4 * (sext i32 %a.deps to…
31 ; CHECK: ArrayDecl[UnknownSize][(sext i32 %a.cols to i64)][(sext i32 %a.deps to i64)] with elements…
41 %p.rows.sext = sext i32 %p.rows.sub to i64
45 %p.cols.sext = sext i32 %p.cols.sub to i64
49 %p.deps.sext = sext i32 %p.deps.sub to i64
52 %a.cols.sext = sext i32 %a.cols to i64
55 %a.deps.sext = sext i32 %a.deps to i64
70 %tmp1 = mul nsw i64 %a.cols.sext, %i
72 %tmp3 = mul i64 %tmp2, %a.deps.sext
77 %k.exitcond = icmp eq i64 %k.inc, %p.deps.sext
[all …]
|
| D | himeno_1.ll | 29 …sext i32 %a.deps to i64) * (1 + (sext i32 %a.cols to i64))) + %a.base),+,(4 * (sext i32 %a.deps to…
31 ; CHECK: ArrayDecl[UnknownSize][(sext i32 %a.cols to i64)][(sext i32 %a.deps to i64)] with elements…
41 %p.rows.sext = sext i32 %p.rows.sub to i64
45 %p.cols.sext = sext i32 %p.cols.sub to i64
49 %p.deps.sext = sext i32 %p.deps.sub to i64
64 %a.cols.sext = sext i32 %a.cols to i64
65 %a.deps.sext = sext i32 %a.deps to i64
70 %tmp1 = mul nsw i64 %a.cols.sext, %i
72 %tmp3 = mul i64 %tmp2, %a.deps.sext
77 %k.exitcond = icmp eq i64 %k.inc, %p.deps.sext
[all …]
|
| /external/llvm/test/Analysis/Delinearization/ |
| D | himeno_2.ll | 29 …sext i32 %a.deps to i64) * (1 + (sext i32 %a.cols to i64))) + %a.base),+,(4 * (sext i32 %a.deps to…
31 ; CHECK: ArrayDecl[UnknownSize][(sext i32 %a.cols to i64)][(sext i32 %a.deps to i64)] with elements…
41 %p.rows.sext = sext i32 %p.rows.sub to i64
45 %p.cols.sext = sext i32 %p.cols.sub to i64
49 %p.deps.sext = sext i32 %p.deps.sub to i64
52 %a.cols.sext = sext i32 %a.cols to i64
55 %a.deps.sext = sext i32 %a.deps to i64
70 %tmp1 = mul nsw i64 %a.cols.sext, %i
72 %tmp3 = mul i64 %tmp2, %a.deps.sext
77 %k.exitcond = icmp eq i64 %k.inc, %p.deps.sext
[all …]
|
| D | himeno_1.ll | 29 …sext i32 %a.deps to i64) * (1 + (sext i32 %a.cols to i64))) + %a.base),+,(4 * (sext i32 %a.deps to…
31 ; CHECK: ArrayDecl[UnknownSize][(sext i32 %a.cols to i64)][(sext i32 %a.deps to i64)] with elements…
41 %p.rows.sext = sext i32 %p.rows.sub to i64
45 %p.cols.sext = sext i32 %p.cols.sub to i64
49 %p.deps.sext = sext i32 %p.deps.sub to i64
64 %a.cols.sext = sext i32 %a.cols to i64
65 %a.deps.sext = sext i32 %a.deps to i64
70 %tmp1 = mul nsw i64 %a.cols.sext, %i
72 %tmp3 = mul i64 %tmp2, %a.deps.sext
77 %k.exitcond = icmp eq i64 %k.inc, %p.deps.sext
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/SystemZ/ |
| D | int-cast.ll | 3 define void @sext() {
4 %v0 = sext i8 undef to i16
5 %v1 = sext i8 undef to i32
6 %v2 = sext i8 undef to i64
7 %v3 = sext i16 undef to i32
8 %v4 = sext i16 undef to i64
9 %v5 = sext i32 undef to i64
10 %v6 = sext <2 x i8> undef to <2 x i16>
11 %v7 = sext <2 x i8> undef to <2 x i32>
12 %v8 = sext <2 x i8> undef to <2 x i64>
[all …]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | vec_sext.ll | 6 %G = sext <4 x i16> %F to <4 x i32>
8 %Y = sext <4 x i16> %H to <4 x i32>
16 %G = sext <4 x i16> %F to <4 x i64>
18 %Y = sext <4 x i16> %H to <4 x i64>
26 %G = sext <4 x i32> %F to <4 x i64>
28 %Y = sext <4 x i32> %H to <4 x i64>
35 %G = sext <4 x i8> %F to <4 x i16>
37 %Y = sext <4 x i8> %H to <4 x i16>
44 %G = sext <4 x i8> %F to <4 x i32>
46 %Y = sext <4 x i8> %H to <4 x i32>
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/ |
| D | shift-sra.ll | 36 ; CHECK-NEXT: [[X2:%.*]] = sext i1 %X to i64
47 %X2 = sext i1 %X to i64
62 ; CHECK-NEXT: [[X2:%.*]] = sext i1 %X to i64
73 %X2 = sext i1 %X to i64
166 ; ashr (sext X), C --> sext (ashr X, C')
171 ; CHECK-NEXT: [[R:%.*]] = sext i8 [[TMP1]] to i32
174 %sext = sext i8 %x to i32
175 %r = ashr i32 %sext, 3
179 ; ashr (sext X), C --> sext (ashr X, C')
184 ; CHECK-NEXT: [[R:%.*]] = sext <2 x i8> [[TMP1]] to <2 x i32>
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/IndVarSimplify/ |
| D | elim-extend.ll | 6 ; IV rewrite only removes one sext. WidenIVs removes all three.
11 ; CHECK-NOT: sext
16 %preofs = sext i32 %iv to i64
20 %postofs = sext i32 %postiv to i64
24 %postofsnsw = sext i32 %postivnsw to i64
43 ; CHECK-NOT: sext
44 ; CHECK: wide.trip.count = sext
45 ; CHECK-NOT: sext
50 %preofs = sext i32 %iv to i64
54 %postofs = sext i32 %postiv to i64
[all …]
|