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Searched refs:shift1 (Results 1 – 25 of 38) sorted by relevance

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/external/owasp/sanitizer/tools/findbugs/bin/
Dfindbugs.bat45 :shift1 label
59 goto shift1
65 goto shift1
71 goto shift1
77 goto shift1
83 goto shift1
89 goto shift1
95 goto shift1
101 goto shift1
107 goto shift1
[all …]
/external/libxaac/decoder/
Dixheaacd_vec_baisc_ops.h24 WORD8 shift1, WORD8 shift2);
28 WORD32 *dest, WORD32 vlen, WORD8 shift1,
35 WORD8 shift1, WORD8 shift2, WORD8 shift3);
41 WORD8 shift1, WORD8 shift2);
58 VOID ixheaacd_scale_down(WORD32 *dest, WORD32 *src, WORD32 len, WORD8 shift1,
Dixheaacd_basic_ops.c78 WORD32 *dest, WORD32 vlen, WORD8 shift1, in ixheaacd_windowing_long1() argument
83 if (shift1 > shift2) { in ixheaacd_windowing_long1()
86 ((ixheaacd_mult32_sh1(*src1, *win_fwd)) >> (shift1 - shift2)), in ixheaacd_windowing_long1()
89 ((ixheaacd_mult32_sh1(-(*src1), *win_rev)) >> (shift1 - shift2)), in ixheaacd_windowing_long1()
104 ((ixheaacd_mult32_sh1(*src2, *win_rev)) >> (shift2 - shift1))); in ixheaacd_windowing_long1()
108 ((ixheaacd_mult32_sh1(*rsrc2, *win_fwd)) >> (shift2 - shift1))); in ixheaacd_windowing_long1()
116 return (shift1); in ixheaacd_windowing_long1()
591 VOID ixheaacd_scale_down(WORD32 *dest, WORD32 *src, WORD32 len, WORD8 shift1, in ixheaacd_scale_down() argument
594 if (shift1 > shift2) { in ixheaacd_scale_down()
596 *dest = *src >> (shift1 - shift2); in ixheaacd_scale_down()
[all …]
Dixheaacd_sbr_dec.c802 WORD shift1, shift2; in ixheaacd_sbr_dec() local
842 shift1 = ptr_sbr_dec->str_sbr_scale_fact.lb_scale + reserve; in ixheaacd_sbr_dec()
845 min_shift = ixheaacd_min32(shift1, shift2); in ixheaacd_sbr_dec()
847 reserve -= (shift1 - min_shift); in ixheaacd_sbr_dec()
/external/webrtc/webrtc/modules/audio_coding/codecs/ilbc/
Ddo_plc.c46 int16_t shift1, shift2, shift3, shiftMax; in WebRtcIlbcfix_DoThePlc() local
108 shift1 = WebRtcSpl_GetSizeInBits(WEBRTC_SPL_ABS_W32(cross_comp))-15; in WebRtcIlbcfix_DoThePlc()
110 (int16_t)WEBRTC_SPL_SHIFT_W32(cross_comp, -shift1) * in WebRtcIlbcfix_DoThePlc()
111 (int16_t)WEBRTC_SPL_SHIFT_W32(cross_comp, -shift1)) >> 15); in WebRtcIlbcfix_DoThePlc()
122 if(((shiftMax<<1)+shift3) > ((shift1<<1)+shift2)) { in WebRtcIlbcfix_DoThePlc()
123 tmp1 = WEBRTC_SPL_MIN(31, (shiftMax<<1)+shift3-(shift1<<1)-shift2); in WebRtcIlbcfix_DoThePlc()
127 tmp2 = WEBRTC_SPL_MIN(31, (shift1<<1)+shift2-(shiftMax<<1)-shift3); in WebRtcIlbcfix_DoThePlc()
135 shiftMax = shift1; in WebRtcIlbcfix_DoThePlc()
/external/llvm/test/CodeGen/ARM/
Dneon_vabs.ll102 %shift1 = ashr <4 x i32> %diff, <i32 31, i32 31, i32 31, i32 31>
103 %add1 = add <4 x i32> %shift1, %diff
104 %res = xor <4 x i32> %shift1, %add1
113 … %shift1 = ashr <8 x i16> %diff,<i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
114 %add1 = add <8 x i16> %shift1, %diff
115 %res = xor <8 x i16> %shift1, %add1
125 %shift1 = ashr <2 x i64> %diff,<i64 63, i64 63>
126 %add1 = add <2 x i64> %shift1, %diff
127 %res = xor <2 x i64> %shift1, %add1
/external/pdfium/core/fxcodec/jbig2/
DJBig2_Image.cpp360 uint32_t shift1 = s1 - d1; in composeTo_opt2() local
361 uint32_t shift2 = 32 - shift1; in composeTo_opt2()
363 uint32_t tmp1 = (JBIG2_GETDWORD(lineSrc) << shift1) | in composeTo_opt2()
397 uint32_t shift1 = s1 - d1; in composeTo_opt2() local
398 uint32_t shift2 = 32 - shift1; in composeTo_opt2()
404 uint32_t tmp1 = (JBIG2_GETDWORD(sp) << shift1) | in composeTo_opt2()
433 uint32_t tmp1 = (JBIG2_GETDWORD(sp) << shift1) | in composeTo_opt2()
463 (JBIG2_GETDWORD(sp) << shift1) | in composeTo_opt2()
584 uint32_t shift1 = d1 - s1; in composeTo_opt2() local
585 uint32_t shift2 = 32 - shift1; in composeTo_opt2()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dneon_vabs.ll159 %shift1 = ashr <4 x i32> %diff, <i32 31, i32 31, i32 31, i32 31>
160 %add1 = add <4 x i32> %shift1, %diff
161 %res = xor <4 x i32> %shift1, %add1
176 … %shift1 = ashr <8 x i16> %diff,<i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
177 %add1 = add <8 x i16> %shift1, %diff
178 %res = xor <8 x i16> %shift1, %add1
194 %shift1 = ashr <2 x i64> %diff,<i64 63, i64 63>
195 %add1 = add <2 x i64> %shift1, %diff
196 %res = xor <2 x i64> %shift1, %add1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Daddsub-shifted.ll10 %shift1 = shl i32 %rhs1, 18
11 %val1 = add i32 %lhs32, %shift1
78 %shift1 = lshr i32 %rhs32, 18
79 %val1 = add i32 %lhs32, %shift1
137 %shift1 = ashr i32 %rhs32, 18
138 %val1 = add i32 %lhs32, %shift1
196 %shift1 = shl i32 %rhs32, 13
197 %tst1 = icmp uge i32 %lhs32, %shift1
248 %shift1 = shl i32 %rhs32, 13
249 %val1 = sub i32 0, %shift1
Dbitfield.ll86 %shift1 = ashr i32 %val32, 31
87 store volatile i32 %shift1, i32* @var32
/external/llvm/test/CodeGen/AArch64/
Daddsub-shifted.ll10 %shift1 = shl i32 %rhs1, 18
11 %val1 = add i32 %lhs32, %shift1
78 %shift1 = lshr i32 %rhs32, 18
79 %val1 = add i32 %lhs32, %shift1
137 %shift1 = ashr i32 %rhs32, 18
138 %val1 = add i32 %lhs32, %shift1
196 %shift1 = shl i32 %rhs32, 13
197 %tst1 = icmp uge i32 %lhs32, %shift1
248 %shift1 = shl i32 %rhs32, 13
249 %val1 = sub i32 0, %shift1
Dbitfield.ll86 %shift1 = ashr i32 %val32, 31
87 store volatile i32 %shift1, i32* @var32
/external/eigen/unsupported/Eigen/CXX11/src/Tensor/
DTensorIntDiv.h138 shift1 = 0;
158 shift1 = log_div > 1 ? 1 : log_div;
169 UnsignedType t = (static_cast<UnsignedType>(numerator) - t1) >> shift1;
176 int32_t shift1;
/external/llvm/test/CodeGen/X86/
Dshift-i256.ll5 ; CHECK-LABEL: shift1
6 define void @shift1(i256 %x, i256 %a, i256* nocapture %r) nounwind readnone {
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dshift-i256.ll5 ; CHECK-LABEL: shift1
6 define void @shift1(i256 %x, i256 %a, i256* nocapture %r) nounwind readnone {
/external/swiftshader/third_party/LLVM/test/Transforms/InstSimplify/
Dexact-nsw-nuw.ll5 ; CHECK: @shift1
7 define i32 @shift1(i32 %A, i32 %B) {
/external/llvm/test/Transforms/InstSimplify/
Dexact-nsw-nuw.ll5 ; CHECK-LABEL: @shift1(
7 define i32 @shift1(i32 %A, i32 %B) {
/external/libopus/silk/
DPLC.c170 static OPUS_INLINE void silk_PLC_energy(opus_int32 *energy1, opus_int *shift1, opus_int32 *energy2,… in silk_PLC_energy() argument
189 silk_sum_sqr_shift( energy1, shift1, exc_buf, subfr_length ); in silk_PLC_energy()
202 opus_int lag, idx, sLTP_buf_idx, shift1, shift2; in silk_PLC_conceal() local
235 …silk_PLC_energy(&energy1, &shift1, &energy2, &shift2, psDec->exc_Q14, prevGain_Q10, psDec->subfr_l… in silk_PLC_conceal()
237 if( silk_RSHIFT( energy1, shift2 ) < silk_RSHIFT( energy2, shift1 ) ) { in silk_PLC_conceal()
/external/webrtc/webrtc/common_audio/signal_processing/
Dvector_scaling_operations.c121 void WebRtcSpl_ScaleAndAddVectors(const int16_t *in1, int16_t gain1, int shift1, in WebRtcSpl_ScaleAndAddVectors() argument
137 *outptr++ = (int16_t)((gain1 * *in1ptr++) >> shift1) + in WebRtcSpl_ScaleAndAddVectors()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/
Dexact-nsw-nuw.ll5 define i32 @shift1(i32 %A, i32 %B) {
6 ; CHECK-LABEL: @shift1(
/external/libaom/libaom/aom_dsp/
Dintrapred.c236 static INLINE int divide_using_multiply_shift(int num, int shift1, in divide_using_multiply_shift() argument
238 const int interm = num >> shift1; in divide_using_multiply_shift()
267 const uint8_t *left, int shift1, in dc_predictor_rect() argument
279 sum + ((bw + bh) >> 1), shift1, multiplier, DC_SHIFT2); in dc_predictor_rect()
584 int shift1, uint32_t multiplier) { in highbd_dc_predictor_rect() argument
596 sum + ((bw + bh) >> 1), shift1, multiplier, HIGHBD_DC_SHIFT2); in highbd_dc_predictor_rect()
/external/guava/guava-tests/test/com/google/common/cache/
DCacheExpirationTest.java402 int shift1 = 10 + VALUE_PREFIX; in runRemovalScheduler() local
403 loader.setValuePrefix(shift1); in runRemovalScheduler()
406 assertEquals(Integer.valueOf(i + shift1), cache.getUnchecked(keyPrefix + i)); in runRemovalScheduler()
417 int shift2 = shift1 + 10; in runRemovalScheduler()
/external/llvm/test/Transforms/SROA/
Dbig-endian.ll32 ; CHECK-NEXT: %[[shift1:.*]] = shl i24 %[[ext1]], 8
34 ; CHECK-NEXT: %[[insert1:.*]] = or i24 %[[mask1]], %[[shift1]]
52 ; CHECK-NEXT: %[[shift1:.*]] = lshr i24 %[[insert0]], 8
53 ; CHECK-NEXT: %[[trunc1:.*]] = trunc i24 %[[shift1]] to i8
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SROA/
Dbig-endian.ll32 ; CHECK-NEXT: %[[shift1:.*]] = shl i24 %[[ext1]], 8
34 ; CHECK-NEXT: %[[insert1:.*]] = or i24 %[[mask1]], %[[shift1]]
52 ; CHECK-NEXT: %[[shift1:.*]] = lshr i24 %[[insert0]], 8
53 ; CHECK-NEXT: %[[trunc1:.*]] = trunc i24 %[[shift1]] to i8
/external/libhevc/decoder/arm/
Dihevcd_itrans_recon_dc_luma.s67 mov r6,#64 @ 1 << (shift1 - 1)@

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