Home
last modified time | relevance | path

Searched refs:shrn (Results 1 – 25 of 50) sorted by relevance

12

/external/libhevc/common/arm64/
Dihevc_inter_pred_luma_vert_w16inp_w16out.s211 shrn v19.4h, v19.4s, #6
230 shrn v20.4h, v20.4s, #6
257 shrn v21.4h, v21.4s, #6
275 shrn v31.4h, v31.4s, #6
302 shrn v19.4h, v19.4s, #6
323 shrn v20.4h, v20.4s, #6
345 shrn v21.4h, v21.4s, #6
360 shrn v31.4h, v31.4s, #6
374 shrn v19.4h, v19.4s, #6
387 shrn v20.4h, v20.4s, #6
[all …]
Dihevc_intra_pred_filters_chroma_mode_19_to_25.s256 shrn v5.8b, v2.8h,#5 //idx = pos >> 5
387 shrn v3.8b, v2.8h,#5 //idx = pos >> 5
488 shrn v3.8b, v2.8h,#5 //idx = pos >> 5
Dihevc_intra_pred_luma_mode_27_to_33.s148 shrn v5.8b, v2.8h,#5 //idx = pos >> 5
281 shrn v3.8b, v2.8h,#5 //idx = pos >> 5
379 shrn v3.8b, v2.8h,#5 //idx = pos >> 5
Dihevc_intra_pred_chroma_mode_27_to_33.s143 shrn v5.8b, v2.8h,#5 //idx = pos >> 5
276 shrn v3.8b, v2.8h,#5 //idx = pos >> 5
373 shrn v3.8b, v2.8h,#5 //idx = pos >> 5
Dihevc_intra_pred_filters_luma_mode_19_to_25.s260 shrn v5.8b, v2.8h,#5 //idx = pos >> 5
387 shrn v3.8b, v2.8h,#5 //idx = pos >> 5
487 shrn v3.8b, v2.8h,#5 //idx = pos >> 5
/external/libavc/encoder/armv8/
Dih264e_half_pel_av8.s374 …shrn v21.4h, v20.4s, #8 //// shift by 8 and later we will shift by 2 more with roundin…
376 …shrn v20.4h, v26.4s, #8 //// shift by 8 and later we will shift by 2 more with roundin…
392 …shrn v28.4h, v2.4s, #8 //// shift by 8 and later we will shift by 2 more with roundin…
399 …shrn v29.4h, v26.4s, #8 //// shift by 8 and later we will shift by 2 more with roundin…
425 …shrn v28.4h, v22.4s, #8 //// shift by 8 and later we will shift by 2 more with roundin…
490 …shrn v21.4h, v20.4s, #8 //// shift by 8 and later we will shift by 2 more with roundin…
492 …shrn v20.4h, v26.4s, #8 //// shift by 8 and later we will shift by 2 more with roundin…
508 …shrn v28.4h, v6.4s, #8 //// shift by 8 and later we will shift by 2 more with roundin…
515 …shrn v29.4h, v26.4s, #8 //// shift by 8 and later we will shift by 2 more with roundin…
540 …shrn v28.4h, v22.4s, #8 //// shift by 8 and later we will shift by 2 more with roundin…
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-vecFold.ll9 ; CHECK: shrn.8b v0, v0, #5
25 ; CHECK: shrn.4h v0, v0, #5
41 ; CHECK: shrn.2s v0, v0, #5
138 declare <8 x i8> @llvm.aarch64.neon.shrn.v8i8(<8 x i16>, i32) nounwind readnone
139 declare <4 x i16> @llvm.aarch64.neon.shrn.v4i16(<4 x i32>, i32) nounwind readnone
140 declare <2 x i32> @llvm.aarch64.neon.shrn.v2i32(<2 x i64>, i32) nounwind readnone
Darm64-neon-simd-shift.ll215 ; CHECK: shrn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, #3
223 ; CHECK: shrn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, #9
231 ; CHECK: shrn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, #19
239 ; CHECK: shrn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, #3
247 ; CHECK: shrn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, #9
255 ; CHECK: shrn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, #19
Darm64-vshift.ll679 ;CHECK: shrn.8b v0, {{v[0-9]+}}, #1
688 ;CHECK: shrn.4h v0, {{v[0-9]+}}, #1
697 ;CHECK: shrn.2s v0, {{v[0-9]+}}, #1
737 declare <8 x i8> @llvm.aarch64.neon.shrn.v8i8(<8 x i16>, i32) nounwind readnone
738 declare <4 x i16> @llvm.aarch64.neon.shrn.v4i16(<4 x i32>, i32) nounwind readnone
739 declare <2 x i32> @llvm.aarch64.neon.shrn.v2i32(<2 x i64>, i32) nounwind readnone
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-vecFold.ll9 ; CHECK: shrn.8b v0, v0, #5
25 ; CHECK: shrn.4h v0, v0, #5
41 ; CHECK: shrn.2s v0, v0, #5
138 declare <8 x i8> @llvm.aarch64.neon.shrn.v8i8(<8 x i16>, i32) nounwind readnone
139 declare <4 x i16> @llvm.aarch64.neon.shrn.v4i16(<4 x i32>, i32) nounwind readnone
140 declare <2 x i32> @llvm.aarch64.neon.shrn.v2i32(<2 x i64>, i32) nounwind readnone
Darm64-neon-simd-shift.ll215 ; CHECK: shrn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, #3
223 ; CHECK: shrn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, #9
231 ; CHECK: shrn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, #19
239 ; CHECK: shrn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, #3
247 ; CHECK: shrn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, #9
255 ; CHECK: shrn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, #19
Darm64-vshift.ll679 ;CHECK: shrn.8b v0, {{v[0-9]+}}, #1
688 ;CHECK: shrn.4h v0, {{v[0-9]+}}, #1
697 ;CHECK: shrn.2s v0, {{v[0-9]+}}, #1
737 declare <8 x i8> @llvm.aarch64.neon.shrn.v8i8(<8 x i16>, i32) nounwind readnone
738 declare <4 x i16> @llvm.aarch64.neon.shrn.v4i16(<4 x i32>, i32) nounwind readnone
739 declare <2 x i32> @llvm.aarch64.neon.shrn.v2i32(<2 x i64>, i32) nounwind readnone
/external/capstone/suite/MC/AArch64/
Dneon-simd-shift.s.cs92 0x20,0x84,0x0d,0x0f = shrn v0.8b, v1.8h, #3
93 0x20,0x84,0x1d,0x0f = shrn v0.4h, v1.4s, #3
94 0x20,0x84,0x3d,0x0f = shrn v0.2s, v1.2d, #3
/external/llvm/test/MC/AArch64/
Dneon-simd-shift.s262 shrn v0.8b, v1.8h, #3
263 shrn v0.4h, v1.4s, #3
264 shrn v0.2s, v1.2d, #3
Darm64-advsimd.s1473 shrn.8b v0, v0, #1
1475 shrn.4h v0, v0, #3
1477 shrn.2s v0, v0, #5
1645 ; CHECK: shrn.8b v0, v0, #1 ; encoding: [0x00,0x84,0x0f,0x0f]
1647 ; CHECK: shrn.4h v0, v0, #3 ; encoding: [0x00,0x84,0x1d,0x0f]
1649 ; CHECK: shrn.2s v0, v0, #5 ; encoding: [0x00,0x84,0x3b,0x0f]
1805 shrn v9.8b, v11.8h, #1
1807 shrn v7.4h, v8.4s, #3
1809 shrn v5.2s, v6.2d, #5
1875 ; CHECK: shrn.8b v9, v11, #1 ; encoding: [0x69,0x85,0x0f,0x0f]
[all …]
Dneon-diagnostics.s1807 shrn v0.8b, v1.8b, #3
1808 shrn v0.4h, v1.4h, #3
1809 shrn v0.2s, v1.2s, #3
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-simd-shift.s262 shrn v0.8b, v1.8h, #3
263 shrn v0.4h, v1.4s, #3
264 shrn v0.2s, v1.2d, #3
Darm64-advsimd.s1473 shrn.8b v0, v0, #1
1475 shrn.4h v0, v0, #3
1477 shrn.2s v0, v0, #5
1645 ; CHECK: shrn.8b v0, v0, #1 ; encoding: [0x00,0x84,0x0f,0x0f]
1647 ; CHECK: shrn.4h v0, v0, #3 ; encoding: [0x00,0x84,0x1d,0x0f]
1649 ; CHECK: shrn.2s v0, v0, #5 ; encoding: [0x00,0x84,0x3b,0x0f]
1805 shrn v9.8b, v11.8h, #1
1807 shrn v7.4h, v8.4s, #3
1809 shrn v5.2s, v6.2d, #5
1875 ; CHECK: shrn.8b v9, v11, #1 ; encoding: [0x69,0x85,0x0f,0x0f]
[all …]
Dneon-diagnostics.s1812 shrn v0.8b, v1.8b, #3
1813 shrn v0.4h, v1.4h, #3
1814 shrn v0.2s, v1.2s, #3
/external/libjpeg-turbo/simd/arm64/
Djsimd_neon.S585 …shrn v2.4h, v18.4s, #16 /* wsptr[DCTSIZE*0] = (int)DESCALE(tmp10 + tmp3, CONST_BITS+PA…
586 …shrn v9.4h, v20.4s, #16 /* wsptr[DCTSIZE*7] = (int)DESCALE(tmp10 - tmp3, CONST_BITS+PA…
587 …shrn v3.4h, v22.4s, #16 /* wsptr[DCTSIZE*1] = (int)DESCALE(tmp11 + tmp2, CONST_BITS+PA…
588 …shrn v8.4h, v24.4s, #16 /* wsptr[DCTSIZE*6] = (int)DESCALE(tmp11 - tmp2, CONST_BITS+PA…
589 …shrn v4.4h, v26.4s, #16 /* wsptr[DCTSIZE*2] = (int)DESCALE(tmp12 + tmp1, CONST_BITS+PA…
590 …shrn v7.4h, v28.4s, #16 /* wsptr[DCTSIZE*5] = (int)DESCALE(tmp12 - tmp1, CONST_BITS+PA…
591 …shrn v5.4h, v14.4s, #16 /* wsptr[DCTSIZE*3] = (int)DESCALE(tmp13 + tmp0, CONST_BITS+PA…
592 …shrn v6.4h, v16.4s, #16 /* wsptr[DCTSIZE*4] = (int)DESCALE(tmp13 - tmp0, CONST_BITS+PA…
2118 shrn v22.4h, v18.4s, #16
2119 shrn v24.4h, v28.4s, #16
[all …]
/external/libavc/common/armv8/
Dih264_resi_trans_quant_av8.s524 shrn v0.4h, v22.4s, #1 //i4_value = (x0 + x1) >> 1;
526 shrn v1.4h, v24.4s, #1 //i4_value = (x0 - x1) >> 1;
/external/v8/src/arm64/
Dsimulator-logic-arm64.cc2109 LogicVRegister Simulator::shrn(VectorFormat vform, LogicVRegister dst, in shrn() function in v8::internal::Simulator
2232 return shrn(vform, dst, src, shift).UnsignedSaturate(vform); in uqshrn()
2760 shrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in addhn()
2796 shrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in subhn()
/external/vixl/src/aarch64/
Dlogic-aarch64.cc2571 LogicVRegister Simulator::shrn(VectorFormat vform, in shrn() function in vixl::aarch64::Simulator
2726 return shrn(vform, dst, src, shift).UnsignedSaturate(vform); in uqshrn()
3481 shrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in addhn()
3525 shrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in subhn()
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt2048 # CHECK: shrn.8b v0, v0, #0x7
2050 # CHECK: shrn.4h v0, v0, #0xd
2052 # CHECK: shrn.2s v0, v0, #0x1b
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt2048 # CHECK: shrn.8b v0, v0, #0x7
2050 # CHECK: shrn.4h v0, v0, #0xd
2052 # CHECK: shrn.2s v0, v0, #0x1b

12