| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | BUFInstructions.td | 136 bits<8> soffset;
144 (ins SReg_128:$srsrc, SCSrc_b32:$soffset,
146 (ins vaddrClass:$vaddr, SReg_128:$srsrc, SCSrc_b32:$soffset,
151 SCSrc_b32:$soffset, offset:$offset, DFMT:$dfmt, NFMT:$nfmt, GLC:$glc,
154 SCSrc_b32:$soffset, offset:$offset, DFMT:$dfmt, NFMT:$nfmt, GLC:$glc,
172 !if(!eq(addrKind, BUFAddrKind.Offset), "off, $srsrc, $dfmt, $nfmt, $soffset",
174 "$vaddr, $srsrc, $dfmt, $nfmt, $soffset offen",
176 "$vaddr, $srsrc, $dfmt, $nfmt, $soffset idxen",
178 "$vaddr, $srsrc, $dfmt, $nfmt, $soffset idxen offen",
180 "$vaddr, $srsrc, $dfmt, $nfmt, $soffset addr64",
[all …]
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| D | SIIntrinsics.td | 26 llvm_i32_ty, // soffset(SGPR)
42 llvm_i32_ty, // soffset(SGPR)
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| D | SILoadStoreOptimizer.cpp | 329 AddrOpName[NumAddresses++] = AMDGPU::OpName::soffset; in findMatchingInst()
334 AddrOpName[NumAddresses++] = AMDGPU::OpName::soffset; in findMatchingInst()
709 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferLoadPair()
812 .add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset)) in mergeBufferStorePair()
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| D | SIRegisterInfo.cpp | 359 assert(TII->getNamedOperand(MI, AMDGPU::OpName::soffset)->getReg() == in resolveFrameIndex()
501 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)) in buildMUBUFOffsetLoadStore()
1034 TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg(), in eliminateFrameIndex()
1055 TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg(), in eliminateFrameIndex()
1132 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() in eliminateFrameIndex()
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| D | GCNHazardRecognizer.cpp | 507 TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in createsVALUHazard()
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| D | SIInstructions.td | 521 SReg_32:$soffset, i32imm:$offset)> {
530 (ins i32imm:$vaddr, SReg_128:$srsrc, SReg_32:$soffset,
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 2157 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
2159 (!cast<MUBUF>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset),
2165 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
2167 (!cast<MUBUF>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset),
2173 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
2175 (!cast<MUBUF>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset),
2181 (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset),
2185 $rsrc, $soffset, (as_i16imm $offset),
2201 (MUBUFIntrinsicOffset i32:$soffset, i16:$offset),
2203 (!cast<MUBUF>(opcode # _OFFSET) $vdata, $rsrc, $soffset, (as_i16imm $offset),
[all …]
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| D | VIInstrFormats.td | 45 bits<8> soffset;
59 let Inst{63-56} = soffset;
74 bits<8> soffset;
89 let Inst{63-56} = soffset;
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| D | SIInstrInfo.td | 117 SDTCisVT<4, i32>, // soffset(SGPR)
2859 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2861 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2873 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2875 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2921 bits<8> soffset;
3030 SCSrc_32:$soffset, offset:$offset, slc:$slc),
3031 name#" $vdata, $vaddr, $srsrc, $soffset addr64$offset$slc", [], 0
3036 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, offset:$offset,
3038 name#" $vdata, off, $srsrc, $soffset$offset$slc", [], 0
[all …]
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| D | SIIntrinsics.td | 28 llvm_i32_ty, // soffset(SGPR)
44 llvm_i32_ty, // soffset(SGPR)
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| D | SIInstrFormats.td | 517 bits<8> soffset;
532 let Inst{63-56} = soffset;
548 bits<8> soffset;
564 let Inst{63-56} = soffset;
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| D | SIInstrInfo.cpp | 160 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) || in areLoadsFromSameBasePtr()
261 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1) in getMemOpBaseRegImmOfs()
2425 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset); in legalizeOperands()
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| /external/flatbuffers/python/flatbuffers/ |
| D | packer.py | 41 soffset = int32 variable
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| D | builder.py | 255 encode.Write(packer.soffset, self.Bytes, objectStart,
269 encode.Write(packer.soffset, self.Bytes, self.Head(),
723 encode.Write(packer.soffset, self.Bytes, self.Head(), x)
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| /external/flatbuffers/lua/flatbuffers/ |
| D | builder.lua | 219 local soffset = self:Offset()
220 if off <= soffset then
221 local off2 = soffset - off + UOffsetT.bytewidth
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.SI.tbuffer.store.ll | 26 define amdgpu_vs void @test1_scalar_offset(i32 %a1, i32 %vaddr, i32 inreg %soffset) {
29 i32 4, i32 %vaddr, i32 %soffset, i32 32, i32 14, i32 4, i32 0, i32 1, i32 1,
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| D | llvm.amdgcn.tbuffer.store.ll | 32 … void @tbuffer_store_scalar_and_imm_offs(<4 x i32> inreg, <4 x float> %vdata, i32 inreg %soffset) {
35 …gcn.tbuffer.store.v4i32(<4 x i32> %in1, <4 x i32> %0, i32 0, i32 0, i32 %soffset, i32 42, i32 5, i…
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| D | mubuf.ll | 71 ; the soffset operand.
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| /external/mesa3d/src/amd/common/ |
| D | ac_llvm_build.h | 203 LLVMValueRef soffset,
215 LLVMValueRef soffset,
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| D | ac_llvm_build.c | 842 LLVMValueRef soffset, in ac_build_buffer_store_dword() argument
866 soffset, inst_offset, glc, slc, in ac_build_buffer_store_dword()
869 soffset, inst_offset + 8, in ac_build_buffer_store_dword()
878 LLVMValueRef offset = soffset; in ac_build_buffer_store_dword()
919 soffset, in ac_build_buffer_store_dword()
950 LLVMValueRef soffset, in ac_build_buffer_load() argument
960 if (soffset) in ac_build_buffer_load()
961 offset = LLVMBuildAdd(ctx->builder, offset, soffset, ""); in ac_build_buffer_load()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | r600_buffer_common.c | 504 unsigned soffset; in r600_buffer_do_flush_region() local
509 soffset = rtransfer->offset + box->x % R600_MAP_BUFFER_ALIGNMENT; in r600_buffer_do_flush_region()
511 u_box_1d(soffset, box->width, &dma_box); in r600_buffer_do_flush_region()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_buffer_common.c | 496 unsigned soffset; in r600_buffer_do_flush_region() local
501 soffset = rtransfer->offset + box->x % R600_MAP_BUFFER_ALIGNMENT; in r600_buffer_do_flush_region()
503 u_box_1d(soffset, box->width, &dma_box); in r600_buffer_do_flush_region()
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | mubuf.ll | 70 ; the soffset operand.
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_shader.c | 1579 LLVMValueRef vtx_offset, soffset; in si_llvm_load_input_gs() local
1632 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0); in si_llvm_load_input_gs()
1635 vtx_offset, soffset, 0, 1, 0, true, false); in si_llvm_load_input_gs()
1638 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0); in si_llvm_load_input_gs()
1641 ctx->i32_0, vtx_offset, soffset, in si_llvm_load_input_gs()
3524 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn, in si_llvm_emit_es_epilogue() local
3563 out_val, 1, NULL, soffset, in si_llvm_emit_es_epilogue()
4309 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn, in si_llvm_emit_vertex() local
4361 voffset, soffset, 0, in si_llvm_emit_vertex()
5730 LLVMValueRef soffset = LLVMConstInt(ctx.i32, in si_generate_gs_copy_shader() local
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
| D | IntrinsicsAMDGPU.td | 823 llvm_i32_ty, // soffset(SGPR)
838 llvm_i32_ty, // soffset(SGPR)
|