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Searched refs:stackSlot2Index (Results 1 – 12 of 12) sorted by relevance

/external/llvm/lib/CodeGen/
DStackSlotColoring.cpp201 int FI = TargetRegisterInfo::stackSlot2Index(li.reg); in InitializeSlots()
260 int FI = TargetRegisterInfo::stackSlot2Index(li->reg); in ColorSlot()
288 int SS = TargetRegisterInfo::stackSlot2Index(li->reg); in ColorSlots()
301 int SS = TargetRegisterInfo::stackSlot2Index(li->reg); in ColorSlots()
DTargetRegisterInfo.cpp51 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); in PrintReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DStackSlotColoring.cpp225 int FI = TargetRegisterInfo::stackSlot2Index(li.reg); in InitializeSlots()
272 int FI = TargetRegisterInfo::stackSlot2Index(li->reg); in ColorSlot()
334 int SS = TargetRegisterInfo::stackSlot2Index(li->reg); in ColorSlots()
347 int SS = TargetRegisterInfo::stackSlot2Index(li->reg); in ColorSlots()
DTargetRegisterInfo.cpp95 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); in printReg()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DStackSlotColoring.cpp221 int FI = TargetRegisterInfo::stackSlot2Index(li.reg); in InitializeSlots()
264 int SS = TargetRegisterInfo::stackSlot2Index(li->reg); in ColorSlotsWithFreeRegs()
353 int FI = TargetRegisterInfo::stackSlot2Index(li->reg); in ColorSlot()
382 int SS = TargetRegisterInfo::stackSlot2Index(li->reg); in ColorSlots()
395 int SS = TargetRegisterInfo::stackSlot2Index(li->reg); in ColorSlots()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DRDFRegisters.h111 return RegMasks.get(TargetRegisterInfo::stackSlot2Index(R)); in getRegMaskBits()
129 return MaskInfos[TargetRegisterInfo::stackSlot2Index(MaskId)].Units; in getMaskUnits()
DHexagonConstExtenders.cpp256 int FI = TargetRegisterInfo::stackSlot2Index(Reg); in operator MachineOperand()
/external/swiftshader/third_party/LLVM/lib/Target/
DTargetRegisterInfo.cpp36 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); in print()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dcext-opt-negative-fi.mir4 # be stored as indices (stackSlot2Index) together with registers and
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetRegisterInfo.h259 static int stackSlot2Index(unsigned Reg) { in stackSlot2Index() function
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h302 static int stackSlot2Index(unsigned Reg) { in stackSlot2Index() function
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h275 static int stackSlot2Index(unsigned Reg) { in stackSlot2Index() function