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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
DnewvalueSameReg.ll29 %sub5.i.i.i = lshr i32 %1, 5
30 %add619.i.i.i = add i32 %sub5.i.i.i, -134217728
31 %sub5.i.pn.i.i = select i1 %2, i32 %add619.i.i.i, i32 %sub5.i.i.i
32 %storemerge2.i.i = getelementptr inbounds i32, i32* %0, i32 %sub5.i.pn.i.i
39 %sub5.i.i.i44 = lshr i32 %1, 5
40 %add619.i.i.i45 = add i32 %sub5.i.i.i44, -134217728
41 %sub5.i.pn.i.i46 = select i1 %3, i32 %add619.i.i.i45, i32 %sub5.i.i.i44
42 %storemerge2.i.i47 = getelementptr inbounds i32, i32* %0, i32 %sub5.i.pn.i.i46
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/GVNHoist/
Dhoist-convergent.ll23 %sub5 = fsub float %max, %a
24 %mul6 = call float @convergent_func(float %sub5, float %div)
53 %sub5 = fsub float %max, %a
54 %mul6 = call float @func(float %sub5, float %div) #0
79 %sub5 = fsub float %max, %a
80 %mul6 = call float @func(float %sub5, float %div)
Dhoist.ll32 %sub5 = fsub float %min, %a
33 %mul6 = fmul float %sub5, %div
81 %sub5 = fsub float %5, %4
82 %mul6 = fmul float %sub5, %div
133 %sub5 = fsub float %5, %4
134 %mul6 = fmul float %sub5, %div
180 %sub5 = fsub float %5, %4
181 %mul6 = fmul float %sub5, %div
298 %sub5 = fsub float %5, %4
299 %mul6 = fmul float %sub5, %div
[all …]
Dhoist-newgvn.ll38 %sub5 = fsub float %5, %4
39 %mul6 = fmul float %sub5, %div
83 %sub5 = fsub float %5, %4
84 %mul6 = fmul float %sub5, %div
/external/llvm/test/Transforms/LoopReroll/
Dnegative.ll17 ;CHECK-NOT: %sub5 = add nsw i32 %len.addr.014, -1
18 ;CHECK-NOT: %sub5 = add nsw i32 %len.addr.014, -2
22 %len.addr.014 = phi i32 [ %len, %while.body.lr.ph ], [ %sub5, %while.body ]
34 %sub5 = add nsw i32 %len.addr.014, -2
35 %cmp = icmp sgt i32 %sub5, 1
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopReroll/
Dnegative.ll17 ;CHECK-NOT: %sub5 = add nsw i32 %len.addr.014, -1
18 ;CHECK-NOT: %sub5 = add nsw i32 %len.addr.014, -2
22 %len.addr.014 = phi i32 [ %len, %while.body.lr.ph ], [ %sub5, %while.body ]
34 %sub5 = add nsw i32 %len.addr.014, -2
35 %cmp = icmp sgt i32 %sub5, 1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dstldst.ll28 %sub5 = add nsw i32 %6, -10
32 … getelementptr inbounds ([32 x i8], [32 x i8]* @.str, i32 0, i32 0), i32 %sub5, i32 %add6, i32 %0,…
33 … %1, i32 %add, i32 %add1, i32 %sub, i32 %add2, i32 %add3, i32 %sub4, i32 %sub5, i32 %add6) nounwind
/external/llvm/test/CodeGen/Mips/
Dstldst.ll28 %sub5 = add nsw i32 %6, -10
32 … getelementptr inbounds ([32 x i8], [32 x i8]* @.str, i32 0, i32 0), i32 %sub5, i32 %add6, i32 %0,…
33 … %1, i32 %add, i32 %add1, i32 %sub, i32 %add2, i32 %add3, i32 %sub4, i32 %sub5, i32 %add6) nounwind
/external/swiftshader/third_party/LLVM/test/Transforms/LoopUnroll/
D2011-08-08-PhiUpdate.ll9 ; CHECK: %sub5.lcssa = phi i32 [ %sub{{.*}}, %if.else{{.*}} ], [ %sub{{.*}}, %if.else{{.*}} ], [ %s…
20 %sub = phi i32 [ %i, %if.else.lr.ph ], [ %sub5, %if.else ]
21 %sub5 = sub i32 %sub, %j
26 %i.tr = phi i32 [ %i, %entry ], [ %sub5, %if.else ]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopUnroll/
D2011-08-08-PhiUpdate.ll9 ; CHECK: %sub5.lcssa = phi i32 [ %sub{{.*}}, %if.else{{.*}} ], [ %sub{{.*}}, %if.else{{.*}} ], [ %s…
20 %sub = phi i32 [ %i, %if.else.lr.ph ], [ %sub5, %if.else ]
21 %sub5 = sub i32 %sub, %j
26 %i.tr = phi i32 [ %i, %entry ], [ %sub5, %if.else ]
/external/llvm/test/Transforms/LoopUnroll/
D2011-08-08-PhiUpdate.ll9 ; CHECK: %sub5.lcssa = phi i32 [ %sub{{.*}}, %if.else{{.*}} ], [ %sub{{.*}}, %if.else{{.*}} ], [ %s…
20 %sub = phi i32 [ %i, %if.else.lr.ph ], [ %sub5, %if.else ]
21 %sub5 = sub i32 %sub, %j
26 %i.tr = phi i32 [ %i, %entry ], [ %sub5, %if.else ]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dcoalescer-subreg-join.mir60 %11.sub5 = COPY %1
69 %20.sub5 = COPY %2
/external/llvm/test/Transforms/InstCombine/
Ddiv-shift-crash.ll69 %sub5.i.i.i.i = sub nsw i32 -701565022, %storemerge.i.i.i
70 %.sub5.i.i.i.i = select i1 %cmp.i.i.i.i, i32 -701565022, i32 %sub5.i.i.i.i
74 %div.i.i.i.i = udiv i32 %conv33.i.i.i, %.sub5.i.i.i.i
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Ddiv-shift-crash.ll69 %sub5.i.i.i.i = sub nsw i32 -701565022, %storemerge.i.i.i
70 %.sub5.i.i.i.i = select i1 %cmp.i.i.i.i, i32 -701565022, i32 %sub5.i.i.i.i
74 %div.i.i.i.i = udiv i32 %conv33.i.i.i, %.sub5.i.i.i.i
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
D2011-12-05-NoSpillDupCR.ll46 %sub5.us = sub i64 31999, %indvars.iv20
47 %sext = shl i64 %sub5.us, 32
81 %sub5.us.1 = sub i64 31999, %indvars.iv20.1
82 %sext23 = shl i64 %sub5.us.1, 32
103 %sub5.us.2 = sub i64 31999, %indvars.iv20.2
104 %sext24 = shl i64 %sub5.us.2, 32
125 %sub5.us.3 = sub i64 31999, %indvars.iv20.3
126 %sext25 = shl i64 %sub5.us.3, 32
147 %sub5.us.4 = sub i64 31999, %indvars.iv20.4
148 %sext26 = shl i64 %sub5.us.4, 32
/external/llvm/test/CodeGen/PowerPC/
D2011-12-05-NoSpillDupCR.ll46 %sub5.us = sub i64 31999, %indvars.iv20
47 %sext = shl i64 %sub5.us, 32
81 %sub5.us.1 = sub i64 31999, %indvars.iv20.1
82 %sext23 = shl i64 %sub5.us.1, 32
103 %sub5.us.2 = sub i64 31999, %indvars.iv20.2
104 %sext24 = shl i64 %sub5.us.2, 32
125 %sub5.us.3 = sub i64 31999, %indvars.iv20.3
126 %sext25 = shl i64 %sub5.us.3, 32
147 %sub5.us.4 = sub i64 31999, %indvars.iv20.4
148 %sext26 = shl i64 %sub5.us.4, 32
/external/clang/test/Sema/
Dtypecheck-binop.c21 int sub5(void *P, int *Q) { in sub5() function
/external/llvm/lib/Target/AMDGPU/
DAMDGPURegisterInfo.cpp42 AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9, in getSubRegFromChannel()
DSIRegisterInfo.td144 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
155 def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
217 def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
228 def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
/external/llvm/test/CodeGen/SystemZ/
Dfp-sub-01.ll111 %sub5 = fsub float %sub4, %val5
112 %sub6 = fsub float %sub5, %val6
Dfp-sub-02.ll113 %sub5 = fsub double %sub4, %val5
114 %sub6 = fsub double %sub5, %val6
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dfp-sub-01.ll113 %sub5 = fsub float %sub4, %val5
114 %sub6 = fsub float %sub5, %val6
Dfp-sub-02.ll113 %sub5 = fsub double %sub4, %val5
114 %sub6 = fsub double %sub5, %val6
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPURegisterInfo.cpp33 AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9, in getSubRegFromChannel()
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Datomic_add.ll195 define void @sub5(i32* nocapture %p) nounwind ssp {
197 ; CHECK: sub5:

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