Searched refs:sysclk_sel (Results 1 – 6 of 6) sorted by relevance
96 u32 sysclk_sel; in get_mcu_main_clk() local99 sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK; in get_mcu_main_clk()100 sysclk_sel >>= MC_CGM_SC_SEL_OFFSET; in get_mcu_main_clk()107 switch (sysclk_sel) { in get_mcu_main_clk()131 u32 sysclk_sel; in get_sys_clk() local145 sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK; in get_sys_clk()146 sysclk_sel >>= MC_CGM_SC_SEL_OFFSET; in get_sys_clk()154 switch (sysclk_sel) { in get_sys_clk()
42 u32 sysclk_sel, pll_pfd_sel = 0; in get_mcu_main_clk() local46 sysclk_sel = ccm_ccsr & CCM_CCSR_SYS_CLK_SEL_MASK; in get_mcu_main_clk()47 sysclk_sel >>= CCM_CCSR_SYS_CLK_SEL_OFFSET; in get_mcu_main_clk()54 switch (sysclk_sel) { in get_mcu_main_clk()
21 u8 sysclk_sel; /* 0x8 - */ member
110 printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); in cpld_dump_regs()
22 u8 sysclk_sel; /* 0x8 - System clock POR Register */ member
103 printf("sysclk_sel = %x\n", CPLD_READ(sysclk_sel)); in cpld_dump_regs()