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Searched refs:tzcnt (Results 1 – 24 of 24) sorted by relevance

/external/llvm/test/CodeGen/X86/
Dlzcnt-tzcnt.ll160 ; CHECK: tzcnt
171 ; CHECK: tzcnt
182 ; CHECK: tzcnt
193 ; CHECK: tzcnt
204 ; CHECK: tzcnt
215 ; CHECK: tzcnt
228 ; CHECK: tzcnt
241 ; CHECK: tzcnt
254 ; CHECK: tzcnt
267 ; CHECK: tzcnt
[all …]
Dvector-tzcnt-128.ll11 ; Just one 32-bit run to make sure we do reasonable things for i64 tzcnt.
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/SkylakeServer/
Dresources-bmi1.s34 tzcnt %eax, %ecx label
35 tzcnt (%rax), %ecx label
37 tzcnt %rax, %rcx label
38 tzcnt (%rax), %rcx label
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/SkylakeClient/
Dresources-bmi1.s34 tzcnt %eax, %ecx label
35 tzcnt (%rax), %ecx label
37 tzcnt %rax, %rcx label
38 tzcnt (%rax), %rcx label
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/Broadwell/
Dresources-bmi1.s34 tzcnt %eax, %ecx label
35 tzcnt (%rax), %ecx label
37 tzcnt %rax, %rcx label
38 tzcnt (%rax), %rcx label
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/Haswell/
Dresources-bmi1.s34 tzcnt %eax, %ecx label
35 tzcnt (%rax), %ecx label
37 tzcnt %rax, %rcx label
38 tzcnt (%rax), %rcx label
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/Generic/
Dresources-bmi1.s34 tzcnt %eax, %ecx label
35 tzcnt (%rax), %ecx label
37 tzcnt %rax, %rcx label
38 tzcnt (%rax), %rcx label
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/Znver1/
Dresources-bmi1.s34 tzcnt %eax, %ecx label
35 tzcnt (%rax), %ecx label
37 tzcnt %rax, %rcx label
38 tzcnt (%rax), %rcx label
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/BtVer2/
Dresources-bmi1.s34 tzcnt %eax, %ecx label
35 tzcnt (%rax), %ecx label
37 tzcnt %rax, %rcx label
38 tzcnt (%rax), %rcx label
/external/libaom/libaom/third_party/libyuv/source/
Dx86inc.asm1134 ; tzcnt is equivalent to "rep bsf" and is backwards-compatible with bsf.
1135 ; This lets us use tzcnt without bumping the yasm version requirement yet.
1136 %define tzcnt rep bsf
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrInfo.td1383 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1387 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1392 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1395 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1400 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1404 "tzcnt{q}\t{$src, $dst|$dst, $src}",
DX86GenAsmWriter1.inc3957 "Call_64\000# TLS_addr32\000# TLS_addr64\000ud2\000ftst\000tzcnt\t\000fu"
/external/v8/src/ia32/
Dassembler-ia32.h1531 void tzcnt(Register dst, Register src) { tzcnt(dst, Operand(src)); } in tzcnt() function
1532 void tzcnt(Register dst, Operand src);
Dmacro-assembler-ia32.cc1563 tzcnt(dst, src); in Tzcnt()
Dassembler-ia32.cc3058 void Assembler::tzcnt(Register dst, Operand src) { in tzcnt() function in v8::internal::Assembler
/external/llvm/lib/Target/X86/
DX86InstrInfo.td2179 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2183 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2188 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2192 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2197 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2201 "tzcnt{q}\t{$src, $dst|$dst, $src}",
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrInfo.td2339 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2343 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2348 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2352 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2357 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2361 "tzcnt{q}\t{$src, $dst|$dst, $src}",
DX86.td282 def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt",
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dclz.ll929 ; This is relevant for 32-bit mode without tzcnt
Dvector-tzcnt-256.ll11 ; Just one 32-bit run to make sure we do reasonable things for i64 tzcnt.
Dvector-tzcnt-128.ll15 ; Just one 32-bit run to make sure we do reasonable things for i64 tzcnt.
/external/epid-sdk/ext/ipp/sources/include/
Dia_32e.inc2032 tzcnt macro x:req, z:req
2033 %ECHO @CatStr(<tzcnt >, < x,>, < z >)
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenAsmMatcher.inc6677 "testq\005testw\006tpause\005tzcnt\006tzcntl\006tzcntq\006tzcntw\005tzms"
23934 { 7849 /* tzcnt */, X86::TZCNT16rr, Convert__Reg1_0__Reg1_1, 0, { MCK_GR16, MCK_GR16 }, },
23935 { 7849 /* tzcnt */, X86::TZCNT16rm, Convert__Reg1_0__Mem165_1, 0, { MCK_GR16, MCK_Mem16 }, },
23936 { 7849 /* tzcnt */, X86::TZCNT32rr, Convert__Reg1_0__Reg1_1, 0, { MCK_GR32, MCK_GR32 }, },
23937 { 7849 /* tzcnt */, X86::TZCNT32rm, Convert__Reg1_0__Mem325_1, 0, { MCK_GR32, MCK_Mem32 }, },
23938 { 7849 /* tzcnt */, X86::TZCNT64rr, Convert__Reg1_0__Reg1_1, 0, { MCK_GR64, MCK_GR64 }, },
23939 { 7849 /* tzcnt */, X86::TZCNT64rm, Convert__Reg1_0__Mem645_1, 0, { MCK_GR64, MCK_Mem64 }, },
DX86GenSubtargetInfo.inc189 …{ "false-deps-lzcnt-tzcnt", "LZCNT/TZCNT have a false dependency on dest register", { X86::Feature…