| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vsqrt.ll | 179 ;CHECK: urecpe.2s
181 %tmp3 = call <2 x i32> @llvm.aarch64.neon.urecpe.v2i32(<2 x i32> %tmp1)
187 ;CHECK: urecpe.4s
189 %tmp3 = call <4 x i32> @llvm.aarch64.neon.urecpe.v4i32(<4 x i32> %tmp1)
193 declare <2 x i32> @llvm.aarch64.neon.urecpe.v2i32(<2 x i32>) nounwind readnone
194 declare <4 x i32> @llvm.aarch64.neon.urecpe.v4i32(<4 x i32>) nounwind readnone
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-vsqrt.ll | 179 ;CHECK: urecpe.2s
181 %tmp3 = call <2 x i32> @llvm.aarch64.neon.urecpe.v2i32(<2 x i32> %tmp1)
187 ;CHECK: urecpe.4s
189 %tmp3 = call <4 x i32> @llvm.aarch64.neon.urecpe.v4i32(<4 x i32> %tmp1)
193 declare <2 x i32> @llvm.aarch64.neon.urecpe.v2i32(<2 x i32>) nounwind readnone
194 declare <4 x i32> @llvm.aarch64.neon.urecpe.v4i32(<4 x i32>) nounwind readnone
|
| /external/capstone/suite/MC/AArch64/ |
| D | neon-simd-misc.s.cs | 195 0x06,0xc9,0xa1,0x4e = urecpe v6.4s, v8.4s
196 0x04,0xc8,0xa1,0x0e = urecpe v4.2s, v0.2s
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-misc.s | 670 urecpe v6.4s, v8.4s
671 urecpe v4.2s, v0.2s
|
| D | neon-diagnostics.s | 5941 urecpe v0.16b, v31.16b
5942 urecpe v2.8h, v4.8h
5943 urecpe v1.8b, v9.8b
5944 urecpe v13.4h, v21.4h
5945 urecpe v1.2d, v9.2d
|
| D | arm64-advsimd.s | 604 urecpe.2s v0, v0
654 ; CHECK: urecpe.2s v0, v0 ; encoding: [0x00,0xc8,0xa1,0x0e]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | neon-simd-misc.s | 670 urecpe v6.4s, v8.4s
671 urecpe v4.2s, v0.2s
|
| D | neon-diagnostics.s | 5881 urecpe v0.16b, v31.16b
5882 urecpe v2.8h, v4.8h
5883 urecpe v1.8b, v9.8b
5884 urecpe v13.4h, v21.4h
5885 urecpe v1.2d, v9.2d
|
| D | arm64-advsimd.s | 604 urecpe.2s v0, v0
654 ; CHECK: urecpe.2s v0, v0 ; encoding: [0x00,0xc8,0xa1,0x0e]
|
| /external/v8/src/arm64/ |
| D | macro-assembler-arm64.h | 348 V(urecpe, Urecpe) \
|
| D | simulator-arm64.h | 1995 LogicVRegister urecpe(VectorFormat vform, LogicVRegister dst,
|
| D | assembler-arm64.h | 2704 void urecpe(const VRegister& vd, const VRegister& vn);
|
| D | simulator-arm64.cc | 3654 urecpe(fpf, rd, rn); in VisitNEON2RegMisc()
|
| D | simulator-logic-arm64.cc | 4094 LogicVRegister Simulator::urecpe(VectorFormat vform, LogicVRegister dst, in urecpe() function in v8::internal::Simulator
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 2967 LogicVRegister urecpe(VectorFormat vform,
|
| D | assembler-aarch64.h | 2887 void urecpe(const VRegister& vd, const VRegister& vn);
|
| D | macro-assembler-aarch64.h | 2740 V(urecpe, Urecpe) \
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 2040 0x~~~~~~~~~~~~~~~~ 0ea1c9f7 urecpe v23.2s, v15.2s
2041 0x~~~~~~~~~~~~~~~~ 4ea1c8fb urecpe v27.4s, v7.4s
|
| D | log-disasm | 2040 0x~~~~~~~~~~~~~~~~ 0ea1c9f7 urecpe v23.2s, v15.2s
2041 0x~~~~~~~~~~~~~~~~ 4ea1c8fb urecpe v27.4s, v7.4s
|
| D | log-cpufeatures-custom | 2039 0x~~~~~~~~~~~~~~~~ 0ea1c9f7 urecpe v23.2s, v15.2s ### {NEON} ###
2040 0x~~~~~~~~~~~~~~~~ 4ea1c8fb urecpe v27.4s, v7.4s ### {NEON} ###
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 2382 __ urecpe(v23.V2S(), v15.V2S()); in GenerateTestSequenceNEON() local
2383 __ urecpe(v27.V4S(), v7.V4S()); in GenerateTestSequenceNEON() local
|
| D | test-simulator-aarch64.cc | 4778 DEFINE_TEST_NEON_2SAME_2S_4S(urecpe, Basic) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 4067 void urecpe(const VRegister& vd, const VRegister& vn)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 503 # CHECK: urecpe.2s v0, v0
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 503 # CHECK: urecpe.2s v0, v0
|