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Searched refs:uxth (Results 1 – 25 of 165) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/
Duxth.s10 uxth z0.s, p0/m, z0.s label
16 uxth z0.d, p0/m, z0.d label
22 uxth z31.s, p7/m, z31.s label
28 uxth z31.d, p7/m, z31.d label
44 uxth z4.d, p7/m, z31.d label
56 uxth z4.d, p7/m, z31.d label
/external/llvm/test/CodeGen/ARM/
Dreturned-ext.ll16 ; CHECKELF: uxth r0, r0
22 ; CHECKT2D: uxth r0, r0
41 ; CHECKELF-NOT: uxth r0, {{r[0-9]+}}
53 ; CHECKT2D-NOT: uxth r0, {{r[0-9]+}}
88 ; CHECKELF: uxth r0, r0
90 ; CHECKELF: uxth r0, r0
94 ; CHECKT2D: uxth r0, r0
96 ; CHECKT2D: uxth r0, r0
112 ; scheduling of uxth and mov instructions below in lieu of the 'returned'
137 ; CHECKELF: uxth r0, r0
[all …]
Dfast-isel-fold.ll25 ; ARM-NOT: uxth
28 ; THUMB-NOT: uxth
54 ; ARM-NOT: uxth
57 ; THUMB-NOT: uxth
Dfast-isel-icmp.ll23 ; ARM: uxth r0, r0
24 ; ARM: uxth r1, r1
27 ; THUMB: uxth r0, r0
28 ; THUMB: uxth r1, r1
Ddagcombine-anyexttozeroext.ll27 ; For now we're generating a vmov.16 and a uxth instruction.
28 ; The uxth is redundant, and we should be able to extend without
32 ; CHECK: uxth
Duxt_rot.ll30 ; CHECK: uxth
31 ; CHECK-NOT: uxth
Dfp16-args.ll31 ; HARD-NOT: uxth
37 ; HARD-NEXT: uxth [[REG1:r[0-9]+]], [[REG0]]
Dfp16-v3.ll14 ; CHECK-NEXT: uxth [[RREG2:r[0-9]+]], [[RREG1]]
35 ; CHECK: uxth
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dreturned-ext.ll16 ; CHECKELF: uxth r0, r0
22 ; CHECKT2D: uxth r0, r0
41 ; CHECKELF-NOT: uxth r0, {{r[0-9]+}}
53 ; CHECKT2D-NOT: uxth r0, {{r[0-9]+}}
88 ; CHECKELF: uxth r0, r0
90 ; CHECKELF: uxth r0, r0
94 ; CHECKT2D: uxth r0, r0
96 ; CHECKT2D: uxth r0, r0
112 ; scheduling of uxth and mov instructions below in lieu of the 'returned'
137 ; CHECKELF: uxth r0, r0
[all …]
Dfast-isel-fold.ll25 ; ARM-NOT: uxth
28 ; THUMB-NOT: uxth
54 ; ARM-NOT: uxth
57 ; THUMB-NOT: uxth
Dfast-isel-icmp.ll23 ; ARM: uxth r0, r0
24 ; ARM: uxth r1, r1
27 ; THUMB: uxth r0, r0
28 ; THUMB: uxth r1, r1
Ddagcombine-anyexttozeroext.ll27 ; For now we're generating a vmov.16 and a uxth instruction.
28 ; The uxth is redundant, and we should be able to extend without
32 ; CHECK: uxth
Dand-load-combine.ll579 ; ARM-NEXT: uxth r1, r1
587 ; ARMEB-NEXT: uxth r1, r1
594 ; THUMB1-NEXT: uxth r1, r1
603 ; THUMB2-NEXT: uxth r1, r1
621 ; ARM-NEXT: uxth r1, r2
631 ; ARMEB-NEXT: uxth r1, r2
642 ; THUMB1-NEXT: uxth r0, r2
652 ; THUMB2-NEXT: uxth r1, r1
673 ; ARM-NEXT: uxth r0, r0
683 ; ARMEB-NEXT: uxth r0, r0
[all …]
Dfp16-v3.ll14 ; CHECK-DAG: uxth [[RREG2:r[0-9]+]], [[RREG1]]
35 ; CHECK: uxth
Dfp16-args.ll31 ; HARD-NOT: uxth
37 ; HARD-NEXT: uxth [[REG1:r[0-9]+]], [[REG0]]
/external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/
Ddiv-vec.ll84 ; ASM: uxth r0, r0
85 ; ASM: uxth r1, r1
87 ; ASM: uxth r0, r0
88 ; ASM: uxth r1, r1
90 ; ASM: uxth r0, r0
91 ; ASM: uxth r1, r1
93 ; ASM: uxth r0, r0
94 ; ASM: uxth r1, r1
96 ; ASM: uxth r0, r0
97 ; ASM: uxth r1, r1
[all …]
/external/llvm/test/MC/AArch64/
Darm64-arithmetic-encoding.s171 add w1, w2, w3, uxth
180 ; CHECK: add w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x0b]
189 add x1, x2, w3, uxth
196 ; CHECK: add x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0x8b]
215 sub w1, w2, w3, uxth
224 ; CHECK: sub w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x4b]
233 sub x1, x2, w3, uxth
240 ; CHECK: sub x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0xcb]
259 adds w1, w2, w3, uxth
268 ; CHECK: adds w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x2b]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Darm64-arithmetic-encoding.s171 add w1, w2, w3, uxth
180 ; CHECK: add w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x0b]
189 add x1, x2, w3, uxth
196 ; CHECK: add x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0x8b]
215 sub w1, w2, w3, uxth
224 ; CHECK: sub w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x4b]
233 sub x1, x2, w3, uxth
240 ; CHECK: sub x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0xcb]
259 adds w1, w2, w3, uxth
268 ; CHECK: adds w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x2b]
[all …]
/external/llvm/test/CodeGen/AArch64/
Daddsub_ext.ll155 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
160 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
167 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
172 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
200 ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, uxth
230 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
235 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
242 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
247 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
Dfast-isel-int-ext2.ll25 ; CHECK-NOT: uxth
53 ; CHECK-NOT: uxth
166 ; CHECK-NOT: uxth
194 ; CHECK-NOT: uxth
308 ; CHECK-NOT: uxth
338 ; CHECK-NOT: uxth
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dthumb.s34 uxth r3, r6
36 @ CHECK: uxth r3, r6 @ encoding: [0xb3,0xb2]
/external/llvm/test/MC/ARM/
Dthumb.s34 uxth r3, r6
36 @ CHECK: uxth r3, r6 @ encoding: [0xb3,0xb2]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dthumb.s34 uxth r3, r6
36 @ CHECK: uxth r3, r6 @ encoding: [0xb3,0xb2]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Daddsub_ext.ll155 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
160 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
167 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
172 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
200 ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, uxth
230 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth
235 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxth #3
242 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth
247 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxth #1
Dfast-isel-int-ext2.ll25 ; CHECK-NOT: uxth
53 ; CHECK-NOT: uxth
166 ; CHECK-NOT: uxth
194 ; CHECK-NOT: uxth
308 ; CHECK-NOT: uxth
338 ; CHECK-NOT: uxth

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