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Searched refs:v2i1 (Results 1 – 25 of 51) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DMachineValueType.h59 v2i1 = 13, // 2 x i1 enumerator
104 FIRST_INTEGER_VECTOR_VALUETYPE = v2i1,
123 FIRST_VECTOR_VALUETYPE = v2i1,
317 case v2i1: in getVectorElementType()
411 case v2i1: in getVectorNumElements()
449 case v2i1: return 2; in getSizeInBits()
593 if (NumElements == 2) return MVT::v2i1; in getVectorVT()
DValueTypes.td36 def v2i1 : ValueType<2 , 13>; // 2 x i1 vector value
/external/llvm/test/Transforms/InstCombine/
Dbitreverse-fold.ll57 %x = call <2 x i1> @llvm.bitreverse.v2i1(<2 x i1> zeroinitializer)
64 %x = call <2 x i1> @llvm.bitreverse.v2i1(<2 x i1> <i1 true, i1 true>)
90 declare <2 x i1> @llvm.bitreverse.v2i1(<2 x i1>) readnone
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/
Dbitreverse-fold.ll71 %x = call <2 x i1> @llvm.bitreverse.v2i1(<2 x i1> zeroinitializer)
78 %x = call <2 x i1> @llvm.bitreverse.v2i1(<2 x i1> <i1 true, i1 true>)
104 declare <2 x i1> @llvm.bitreverse.v2i1(<2 x i1>) readnone
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DMachineValueType.h61 v2i1 = 15, // 2 x i1 enumerator
421 case v2i1: in getVectorElementType()
586 case v2i1: in getVectorNumElements()
646 case v2i1: in getSizeInBits()
833 if (NumElements == 2) return MVT::v2i1; in getVectorVT()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoVector.td14 def V2I1: PatLeaf<(v2i1 PredRegs:$R)>;
227 def: vcmp_vi1_pat<A2_vcmpweq, seteq, V2I32, v2i1>;
228 def: vcmp_vi1_pat<A2_vcmpwgt, setgt, V2I32, v2i1>;
229 def: vcmp_vi1_pat<A2_vcmpwgtu, setugt, V2I32, v2i1>;
311 def: InvertCmp_pat<A2_vcmpwgt, setlt, V2I32, v2i1>;
318 def: InvertCmp_pat<A2_vcmpwgtu, setult, V2I32, v2i1>;
322 def: Pat<(v2i1 (setne V2I32:$Rs, V2I32:$Rt)),
323 (C2_not (v2i1 (A2_vcmpbeq V2I32:$Rs, V2I32:$Rt)))>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DValueTypes.cpp141 case MVT::v2i1: return "v2i1"; in getEVTString()
222 case MVT::v2i1: return VectorType::get(Type::getInt1Ty(Context), 2); in getTypeForEVT()
/external/llvm/lib/IR/
DValueTypes.cpp145 case MVT::v2i1: return "v2i1"; in getEVTString()
223 case MVT::v2i1: return VectorType::get(Type::getInt1Ty(Context), 2); in getTypeForEVT()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td323 def maskzeroupperv2i1 : maskzeroupper<v2i1, VK2>;
414 (v2i1 VK2:$mask), (iPTR 0))),
441 (v2i1 VK2:$mask), (iPTR 0))),
491 (v2i1 VK2:$mask), (iPTR 0))),
504 (v2i1 VK2:$mask), (iPTR 0))),
/external/llvm/test/CodeGen/SystemZ/
Dvec-move-16.ll63 ; Test a v2i1->v2i64 extension.
Dvec-move-15.ll63 ; Test a v2i1->v2i64 extension.
Dvec-move-17.ll63 ; Test a v2i64->v2i1 truncation.
Dvec-and-03.ll71 ; Test a v2i1->v2i64 extension.
Dvec-shift-07.ll71 ; Test a v2i1->v2i64 extension.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dvec-move-15.ll63 ; Test a v2i1->v2i64 extension.
Dvec-move-16.ll63 ; Test a v2i1->v2i64 extension.
Dvec-and-03.ll71 ; Test a v2i1->v2i64 extension.
Dvec-move-17.ll63 ; Test a v2i64->v2i1 truncation.
Dvec-shift-07.ll71 ; Test a v2i1->v2i64 extension.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonPatterns.td81 def V2I1: PatLeaf<(v2i1 PredRegs:$R)>;
487 def: OpR_RR_pat<MI, Op, v2i1, V2I1>;
575 def: OpR_RR_pat<A2_vcmpweq, seteq, v2i1, V2I32>;
577 def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, v2i1, V2I32>;
579 def: OpR_RR_pat<A2_vcmpwgt, setgt, v2i1, V2I32>;
581 def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, v2i1, V2I32>;
583 def: OpR_RR_pat<A2_vcmpwgtu, setugt, v2i1, V2I32>;
649 def: OpmR_RR_pat<Outn<A2_vcmpweq>, setne, v2i1, V2I32>;
650 def: OpmR_RR_pat<Outn<A2_vcmpwgt>, setle, v2i1, V2I32>;
651 def: OpmR_RR_pat<Outn<A2_vcmpwgtu>, setule, v2i1, V2I32>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp89 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
90 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
91 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
118 setTruncStoreAction(MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
184 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); in R600TargetLowering()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DValueTypes.td37 def v2i1 : ValueType<2 , 15>; // 2 x i1 vector value
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp67 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
68 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
69 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
85 setTruncStoreAction(MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Expand); in R600TargetLowering()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp73 case MVT::v2i1: return "MVT::v2i1"; in getEnumName()
/external/llvm/lib/Target/X86/
DX86CallingConv.td46 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
323 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
596 CCIfType<[v2i1], CCPromoteToType<v2i64>>,

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