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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneon-reciprocal-encoding.s3 @ CHECK: vrecpe.u32 d16, d16 @ encoding: [0x20,0x04,0xfb,0xf3]
4 vrecpe.u32 d16, d16
5 @ CHECK: vrecpe.u32 q8, q8 @ encoding: [0x60,0x04,0xfb,0xf3]
6 vrecpe.u32 q8, q8
7 @ CHECK: vrecpe.f32 d16, d16 @ encoding: [0x20,0x05,0xfb,0xf3]
8 vrecpe.f32 d16, d16
9 @ CHECK: vrecpe.f32 q8, q8 @ encoding: [0x60,0x05,0xfb,0xf3]
10 vrecpe.f32 q8, q8
Dneont2-reciprocal-encoding.s5 @ CHECK: vrecpe.u32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x04]
6 vrecpe.u32 d16, d16
7 @ CHECK: vrecpe.u32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x04]
8 vrecpe.u32 q8, q8
9 @ CHECK: vrecpe.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x05]
10 vrecpe.f32 d16, d16
11 @ CHECK: vrecpe.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x05]
12 vrecpe.f32 q8, q8
Dfullfp16-neon.s226 vrecpe.f16 d0, d1
227 vrecpe.f16 q0, q1
228 @ ARM: vrecpe.f16 d0, d1 @ encoding: [0x01,0x05,0xb7,0xf3]
229 @ ARM: vrecpe.f16 q0, q1 @ encoding: [0x42,0x05,0xb7,0xf3]
230 @ THUMB: vrecpe.f16 d0, d1 @ encoding: [0xb7,0xff,0x01,0x05]
231 @ THUMB: vrecpe.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x05]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-reciprocal-encoding.s3 @ CHECK: vrecpe.u32 d16, d16 @ encoding: [0x20,0x04,0xfb,0xf3]
4 vrecpe.u32 d16, d16
5 @ CHECK: vrecpe.u32 q8, q8 @ encoding: [0x60,0x04,0xfb,0xf3]
6 vrecpe.u32 q8, q8
7 @ CHECK: vrecpe.f32 d16, d16 @ encoding: [0x20,0x05,0xfb,0xf3]
8 vrecpe.f32 d16, d16
9 @ CHECK: vrecpe.f32 q8, q8 @ encoding: [0x60,0x05,0xfb,0xf3]
10 vrecpe.f32 q8, q8
Dneont2-reciprocal-encoding.s5 @ CHECK: vrecpe.u32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x04]
6 vrecpe.u32 d16, d16
7 @ CHECK: vrecpe.u32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x04]
8 vrecpe.u32 q8, q8
9 @ CHECK: vrecpe.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x05]
10 vrecpe.f32 d16, d16
11 @ CHECK: vrecpe.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x05]
12 vrecpe.f32 q8, q8
/external/llvm/test/MC/ARM/
Dneon-reciprocal-encoding.s3 @ CHECK: vrecpe.u32 d16, d16 @ encoding: [0x20,0x04,0xfb,0xf3]
4 vrecpe.u32 d16, d16
5 @ CHECK: vrecpe.u32 q8, q8 @ encoding: [0x60,0x04,0xfb,0xf3]
6 vrecpe.u32 q8, q8
7 @ CHECK: vrecpe.f32 d16, d16 @ encoding: [0x20,0x05,0xfb,0xf3]
8 vrecpe.f32 d16, d16
9 @ CHECK: vrecpe.f32 q8, q8 @ encoding: [0x60,0x05,0xfb,0xf3]
10 vrecpe.f32 q8, q8
Dneont2-reciprocal-encoding.s5 @ CHECK: vrecpe.u32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x04]
6 vrecpe.u32 d16, d16
7 @ CHECK: vrecpe.u32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x04]
8 vrecpe.u32 q8, q8
9 @ CHECK: vrecpe.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x05]
10 vrecpe.f32 d16, d16
11 @ CHECK: vrecpe.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x05]
12 vrecpe.f32 q8, q8
Dfullfp16-neon.s226 vrecpe.f16 d0, d1
227 vrecpe.f16 q0, q1
228 @ ARM: vrecpe.f16 d0, d1 @ encoding: [0x01,0x05,0xb7,0xf3]
229 @ ARM: vrecpe.f16 q0, q1 @ encoding: [0x42,0x05,0xb7,0xf3]
230 @ THUMB: vrecpe.f16 d0, d1 @ encoding: [0xb7,0xff,0x01,0x05]
231 @ THUMB: vrecpe.f16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x05]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvrec.ll5 ;CHECK: vrecpe.u32
7 %tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
13 ;CHECK: vrecpe.u32
15 %tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
21 ;CHECK: vrecpe.f32
23 %tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
29 ;CHECK: vrecpe.f32
31 %tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
35 declare <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32>) nounwind readnone
36 declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) nounwind readnone
[all …]
Dneon_div.ll12 ; CHECK: vrecpe.f32
14 ; CHECK: vrecpe.f32
26 ; CHECK: vrecpe.f32
29 ; CHECK: vrecpe.f32
42 ; CHECK: vrecpe.f32
54 ; CHECK: vrecpe.f32
D2009-10-02-NEONSubregsBug.ll38 …%29 = tail call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> zeroinitializer) nounwind ; <<…
63 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
Dvector-extend-narrow.ll57 ; CHECK: vrecpe
D2012-01-23-PostRA-LICM.ll32 %tmp16 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp11) nounwind
101 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
/external/llvm/test/CodeGen/ARM/
Dvrec.ll5 ;CHECK: vrecpe.u32
7 %tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
13 ;CHECK: vrecpe.u32
15 %tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
21 ;CHECK: vrecpe.f32
23 %tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
29 ;CHECK: vrecpe.f32
31 %tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
35 declare <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32>) nounwind readnone
36 declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) nounwind readnone
[all …]
Dneon_div.ll5 ;CHECK: vrecpe.f32
7 ;CHECK: vrecpe.f32
17 ;CHECK: vrecpe.f32
20 ;CHECK: vrecpe.f32
31 ;CHECK: vrecpe.f32
41 ;CHECK: vrecpe.f32
D2009-10-02-NEONSubregsBug.ll38 …%29 = tail call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> zeroinitializer) nounwind ; <<…
63 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
Dvector-extend-narrow.ll57 ; CHECK: vrecpe
D2012-01-23-PostRA-LICM.ll32 %tmp16 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp11) nounwind
101 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvrec.ll5 ;CHECK: vrecpe.u32
7 %tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
13 ;CHECK: vrecpe.u32
15 %tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
21 ;CHECK: vrecpe.f32
23 %tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
29 ;CHECK: vrecpe.f32
31 %tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
35 declare <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32>) nounwind readnone
36 declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) nounwind readnone
[all …]
Dneon_div.ll4 ;CHECK: vrecpe.f32
5 ;CHECK: vrecpe.f32
16 ;CHECK: vrecpe.f32
18 ;CHECK: vrecpe.f32
30 ;CHECK: vrecpe.f32
40 ;CHECK: vrecpe.f32
D2009-10-02-NEONSubregsBug.ll38 …%29 = tail call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> zeroinitializer) nounwind ; <<…
63 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
/external/capstone/suite/MC/ARM/
Dneon-reciprocal-encoding.s.cs2 0x20,0x04,0xfb,0xf3 = vrecpe.u32 d16, d16
3 0x60,0x04,0xfb,0xf3 = vrecpe.u32 q8, q8
4 0x20,0x05,0xfb,0xf3 = vrecpe.f32 d16, d16
5 0x60,0x05,0xfb,0xf3 = vrecpe.f32 q8, q8
Dneont2-reciprocal-encoding.s.cs2 0xfb,0xff,0x20,0x04 = vrecpe.u32 d16, d16
3 0xfb,0xff,0x60,0x04 = vrecpe.u32 q8, q8
4 0xfb,0xff,0x20,0x05 = vrecpe.f32 d16, d16
5 0xfb,0xff,0x60,0x05 = vrecpe.f32 q8, q8
/external/arm-neon-tests/
Dref_vrecpe.c43 vrecpe##Q##_##T2##W(VECT_VAR(vector, T1, W, N)); \ in exec_vrecpe()
DMakefile.gcc60 vqrshrun_n vstX_lane vtbX vrecpe vrsqrte vcage vcagt vcale \

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