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/external/llvm/test/CodeGen/AArch64/
Darm64-ldp-cluster.ll9 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
10 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
14 ; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
15 ; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
29 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRSWui
30 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRSWui
34 ; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRSWui
35 ; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRSWui
50 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDURWi
51 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDURWi
[all …]
Dtailcall_misched_graph.ll29 ; CHECK: [[VRA:%vreg.*]]<def> = LDRXui <fi#-1>
30 ; CHECK: [[VRB:%vreg.*]]<def> = LDRXui <fi#-2>
31 ; CHECK: STRXui %vreg{{.*}}, <fi#-4>
43 ; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}}, <fi#-4>
44 ; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}}, <fi#-3>
Darm64-fast-isel-rem.ll7 ; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]]<def> = SDIVWr
9 ; CHECK-SSA: {{%vreg[0-9]+}}<def> = MSUBWrrr [[QUOTREG]]
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DRegAllocPBQP.h54 void recordVReg(unsigned vreg, PBQP::Graph::NodeItr node, in recordVReg() argument
57 assert(vreg2Node.find(vreg) == vreg2Node.end() && "Re-mapping vreg."); in recordVReg()
58 assert(allowedSets[vreg].empty() && "vreg already has pregs."); in recordVReg()
60 node2VReg[node] = vreg; in recordVReg()
61 vreg2Node[vreg] = node; in recordVReg()
62 std::copy(arBegin, arEnd, std::back_inserter(allowedSets[vreg])); in recordVReg()
69 PBQP::Graph::NodeItr getNodeForVReg(unsigned vreg) const;
73 bool isPRegOption(unsigned vreg, unsigned option) const { in isPRegOption() argument
76 return !isSpillOption(vreg, option); in isPRegOption()
81 bool isSpillOption(unsigned vreg, unsigned option) const { in isSpillOption() argument
[all …]
/external/v8/src/compiler/
Dlive-range-separator.cc50 DCHECK_NULL(data->live_ranges()[splinter->vreg()]); in CreateSplinter()
51 data->live_ranges()[splinter->vreg()] = splinter; in CreateSplinter()
55 TRACE("creating splinter for range %d between %d and %d\n", range->vreg(), in CreateSplinter()
124 for (size_t vreg = 0; vreg < virt_reg_count; ++vreg) { in Splinter() local
125 TopLevelLiveRange *range = data()->live_ranges()[vreg]; in Splinter()
171 int to_remove = range->vreg(); in Merge()
Dregister-allocator-verifier.h95 bool IsAliasOf(int vreg) const { return aliases_.count(vreg) > 0; } in IsAliasOf() argument
96 void AddAlias(int vreg) { aliases_.insert(vreg); } in AddAlias() argument
221 void AddDelayedAssessment(InstructionOperand op, int vreg) { in AddDelayedAssessment() argument
224 map_.insert(std::make_pair(op, vreg)); in AddDelayedAssessment()
226 CHECK_EQ(it->second, vreg); in AddDelayedAssessment()
Dregister-allocator-verifier.cc163 int vreg = unallocated->virtual_register(); in BuildConstraint() local
164 constraint->virtual_register_ = vreg; in BuildConstraint()
172 if (sequence()->IsFP(vreg)) { in BuildConstraint()
179 DCHECK(!sequence()->IsFP(vreg)); in BuildConstraint()
196 if (sequence()->IsFP(vreg)) { in BuildConstraint()
205 ElementSizeLog2Of(sequence()->GetRepresentation(vreg)); in BuildConstraint()
547 int vreg = pair.second; in VerifyGapMoves() local
553 vreg); in VerifyGapMoves()
558 vreg); in VerifyGapMoves()
Dregister-allocator.cc831 TopLevelLiveRange::TopLevelLiveRange(int vreg, MachineRepresentation rep) in TopLevelLiveRange() argument
833 vreg_(vreg), in TopLevelLiveRange()
849 return IsSplinter() ? splintered_from()->vreg() : vreg(); in debug_virt_reg()
1091 TRACE("Shorten live range %d to [%d\n", vreg(), start.value()); in ShortenTo()
1101 TRACE("Ensure live range %d in interval [%d %d[\n", vreg(), start.value(), in EnsureInterval()
1122 TRACE("Add to live range %d interval [%d %d[\n", vreg(), start.value(), in AddUseInterval()
1149 TRACE("Add to live range %d use position %d\n", vreg(), pos.value()); in AddUsePosition()
1195 os << "Range: " << range->TopLevel()->vreg() << ":" << range->relative_id() in operator <<()
1317 os << range->vreg() << " "; in Print()
1429 int vreg = virtual_register_count_++; in GetNextLiveRangeId() local
[all …]
Dinstruction-selector-impl.h239 InstructionOperand DefineSameAsFirstForVreg(int vreg) { in DefineSameAsFirstForVreg() argument
240 return UnallocatedOperand(UnallocatedOperand::SAME_AS_FIRST_INPUT, vreg); in DefineSameAsFirstForVreg()
243 InstructionOperand DefineAsRegistertForVreg(int vreg) { in DefineAsRegistertForVreg() argument
244 return UnallocatedOperand(UnallocatedOperand::MUST_HAVE_REGISTER, vreg); in DefineAsRegistertForVreg()
247 InstructionOperand UseRegisterForVreg(int vreg) { in UseRegisterForVreg() argument
249 UnallocatedOperand::USED_AT_START, vreg); in UseRegisterForVreg()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegAllocPBQP.cpp169 PBQP::Graph::NodeItr PBQPRAProblem::getNodeForVReg(unsigned vreg) const { in getNodeForVReg()
170 VReg2Node::const_iterator nodeItr = vreg2Node.find(vreg); in getNodeForVReg()
177 PBQPRAProblem::getAllowedSet(unsigned vreg) const { in getAllowedSet()
178 AllowedSetMap::const_iterator allowedSetItr = allowedSets.find(vreg); in getAllowedSet()
184 unsigned PBQPRAProblem::getPRegForOption(unsigned vreg, unsigned option) const { in getPRegForOption() argument
185 assert(isPRegOption(vreg, option) && "Not a preg option."); in getPRegForOption()
187 const AllowedSet& allowedSet = getAllowedSet(vreg); in getPRegForOption()
220 unsigned vreg = *vregItr; in build() local
221 const TargetRegisterClass *trc = mri->getRegClass(vreg); in build()
222 const LiveInterval *vregLI = &lis->getInterval(vreg); in build()
[all …]
/external/bcc/src/lua/bpf/
Dbuiltins.lua79 e.emit(BPF.ALU + BPF.END + BPF.TO_BE, e.vreg(dst), 0, 0, w)
87 e.emit(BPF.ALU + BPF.END + BPF.TO_LE, e.vreg(dst), 0, 0, w)
114 local src_reg = e.vreg(b)
115 local dst_reg = e.vreg(a)
118 e.vreg(ret, 0, true, ffi.typeof('int32_t'))
152 e.vreg(src, 3)
161 e.vreg(ret, 0, true, ffi.typeof('int32_t'))
227 e.vreg(src, 3)
232 e.vreg(ret, 0, true, ffi.typeof('int32_t'))
271 e.vreg(e.tmpvar, 3+i-1) -- Materialize it in arg register
[all …]
Dbpf.lua197 local function vreg(var, reg, reserve, vtype) function
300 src_reg = vreg(a)
307 src_reg = vreg(a)
316 src_reg = vreg(a)
330 vreg(i)
337 vreg(i, Vcomp[i].reg)
383 local a_reg, b_reg = vreg(a), vreg(b)
410 local reg = vreg(a)
440 local dst_reg = vreg(dst)
460 local src_reg = b and vreg(b) or 0 -- SRC is optional for unary operations
[all …]
Dproto.lua229 dst_reg = e.vreg(var, 0, true)
233 tmp_reg = e.vreg(e.tmpvar, 0, true, type) -- Reserve R0 for temporary relative offset
234 dst_reg = e.vreg(var) -- Must rematerialize (if it was spilled by tmp var)
263 local dst_reg = e.vreg(var)
/external/v8/src/arm64/
Dsimulator-arm64.cc1221 ? vreg(code).Get<float>(lane) in PrintVRegisterFPHelper()
1222 : vreg(code).Get<double>(lane); in PrintVRegisterFPHelper()
2735 SimVRegister& rd = vreg(instr->Rd()); in VisitFPDataProcessing1Source()
2736 SimVRegister& rn = vreg(instr->Rn()); in VisitFPDataProcessing1Source()
2751 fabs_(vform, vreg(fd), vreg(fn)); in VisitFPDataProcessing1Source()
2757 fneg(vform, vreg(fd), vreg(fn)); in VisitFPDataProcessing1Source()
2826 SimVRegister& rd = vreg(instr->Rd()); in VisitFPDataProcessing2Source()
2827 SimVRegister& rn = vreg(instr->Rn()); in VisitFPDataProcessing2Source()
2828 SimVRegister& rm = vreg(instr->Rm()); in VisitFPDataProcessing2Source()
3467 SimVRegister& rd = vreg(instr->Rd()); in VisitNEON2RegMisc()
[all …]
/external/mesa3d/src/gallium/drivers/r600/sb/
Dsb_bc_finalize.cpp516 unsigned vreg = v->gpr.sel(); in copy_fetch_src() local
520 reg = vreg; in copy_fetch_src()
521 else if ((unsigned)reg != vreg) { in copy_fetch_src()
623 unsigned vreg = v->gpr.sel(); in finalize_fetch() local
627 reg = vreg; in finalize_fetch()
628 else if ((unsigned)reg != vreg) { in finalize_fetch()
670 unsigned vreg = v->gpr.sel(); in finalize_fetch() local
674 reg = vreg; in finalize_fetch()
675 else if ((unsigned)reg != vreg) { in finalize_fetch()
747 unsigned vreg = v->gpr.sel(); in finalize_cf() local
[all …]
/external/v8/src/x64/
Dassembler-x64-inl.h190 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, in emit_vex_prefix() argument
196 emit_vex3_byte2(w, vreg, l, pp); in emit_vex_prefix()
199 emit_vex2_byte1(reg, vreg, l, pp); in emit_vex_prefix()
204 void Assembler::emit_vex_prefix(Register reg, Register vreg, Register rm, in emit_vex_prefix() argument
208 XMMRegister ivreg = XMMRegister::from_code(vreg.code()); in emit_vex_prefix()
213 void Assembler::emit_vex_prefix(XMMRegister reg, XMMRegister vreg, Operand rm, in emit_vex_prefix() argument
219 emit_vex3_byte2(w, vreg, l, pp); in emit_vex_prefix()
222 emit_vex2_byte1(reg, vreg, l, pp); in emit_vex_prefix()
226 void Assembler::emit_vex_prefix(Register reg, Register vreg, Operand rm, in emit_vex_prefix() argument
230 XMMRegister ivreg = XMMRegister::from_code(vreg.code()); in emit_vex_prefix()
/external/u-boot/board/compulab/cm_t54/
Dcm_t54.c55 static int cm_t54_palmas_regulator_set(u8 vreg, u8 vval, u8 creg, u8 cval) in cm_t54_palmas_regulator_set() argument
60 err = palmas_i2c_write_u8(TWL603X_CHIP_P1, vreg, vval); in cm_t54_palmas_regulator_set()
63 vreg, err); in cm_t54_palmas_regulator_set()
/external/llvm/test/CodeGen/ARM/
Dmisched-copy-arm.ll36 ; CHECK: %[[R4:vreg[0-9]+]]<def>, %[[R1:vreg[0-9]+]]<def,tied2> = t2LDR_PRE %[[R1]]<tied1>
37 ; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R1]]
38 ; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R4]]
Dfast-isel-shift-materialize.ll6 ; When materializing the '2' for the shifts below, the second shift kills the vreg
7 ; we materialize in to. However, the first shift was also killing that vreg.
Dfast-isel-remat-same-constant.ll7 ; generated by the GEPs. The first add generated killed the vreg for the #6680 constant which shou…
9 ; down. This meant the next use of the vreg for #6680 was after the first which had killed it.
/external/llvm/test/CodeGen/PowerPC/
Dquadint-return.ll17 ; CHECK: %X3<def> = COPY %vreg
18 ; CHECK-NEXT: %X4<def> = COPY %vreg
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dfast-isel-shift-materialize.ll6 ; When materializing the '2' for the shifts below, the second shift kills the vreg
7 ; we materialize in to. However, the first shift was also killing that vreg.
Dfast-isel-remat-same-constant.ll7 ; generated by the GEPs. The first add generated killed the vreg for the #6680 constant which shou…
9 ; down. This meant the next use of the vreg for #6680 was after the first which had killed it.
/external/vixl/test/aarch64/
Dtest-utils-aarch64.cc186 const VRegister& vreg) { in Equal128() argument
187 VIXL_ASSERT(vreg.Is128Bits()); in Equal128()
189 vec128_t result = core->qreg(vreg.GetCode()); in Equal128()
251 const VRegister& vreg) { in Equal64() argument
252 VIXL_ASSERT(vreg.Is64Bits()); in Equal64()
253 uint64_t result = core->dreg_bits(vreg.GetCode()); in Equal64()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMIRCanonicalizerPass.cpp523 for (auto &vreg : VRegs) { in GetVRegRenameMap() local
524 if (vreg.isFrameIndex()) { in GetVRegRenameMap()
533 } else if (vreg.isCandidate()) { in GetVRegRenameMap()
545 } else if (!TargetRegisterInfo::isVirtualRegister(vreg.getReg())) { in GetVRegRenameMap()
554 auto Reg = vreg.getReg(); in GetVRegRenameMap()

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