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Searched refs:vrev16 (Results 1 – 25 of 36) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneon-reverse-encoding.s23 @ CHECK: vrev16.8 d16, d16 @ encoding: [0x20,0x01,0xf0,0xf3]
24 vrev16.8 d16, d16
25 @ CHECK: vrev16.8 q8, q8 @ encoding: [0x60,0x01,0xf0,0xf3]
26 vrev16.8 q8, q8
Dneont2-reverse-encoding.s23 @ CHECK: vrev16.8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x01]
24 vrev16.8 d16, d16
25 @ CHECK: vrev16.8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x01]
26 vrev16.8 q8, q8
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-reverse-encoding.s23 @ CHECK: vrev16.8 d16, d16 @ encoding: [0x20,0x01,0xf0,0xf3]
24 vrev16.8 d16, d16
25 @ CHECK: vrev16.8 q8, q8 @ encoding: [0x60,0x01,0xf0,0xf3]
26 vrev16.8 q8, q8
Dneont2-reverse-encoding.s23 @ CHECK: vrev16.8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x01]
24 vrev16.8 d16, d16
25 @ CHECK: vrev16.8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x01]
26 vrev16.8 q8, q8
/external/llvm/test/MC/ARM/
Dneon-reverse-encoding.s23 @ CHECK: vrev16.8 d16, d16 @ encoding: [0x20,0x01,0xf0,0xf3]
24 vrev16.8 d16, d16
25 @ CHECK: vrev16.8 q8, q8 @ encoding: [0x60,0x01,0xf0,0xf3]
26 vrev16.8 q8, q8
Dneont2-reverse-encoding.s23 @ CHECK: vrev16.8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x01]
24 vrev16.8 d16, d16
25 @ CHECK: vrev16.8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x01]
26 vrev16.8 q8, q8
/external/capstone/suite/MC/ARM/
Dneon-reverse-encoding.s.cs12 0x20,0x01,0xf0,0xf3 = vrev16.8 d16, d16
13 0x60,0x01,0xf0,0xf3 = vrev16.8 q8, q8
Dneont2-reverse-encoding.s.cs12 0xf0,0xff,0x20,0x01 = vrev16.8 d16, d16
13 0xf0,0xff,0x60,0x01 = vrev16.8 q8, q8
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dbig-endian-neon-extend.ll6 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
36 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
65 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
Dpopcnt.ll23 ; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
35 ; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
47 ; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
62 ; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
Dbig-endian-neon-trunc-store.ll18 ; CHECK: vrev16.8 [[REG]], [[REG]]
Dvrev.ll101 ;CHECK: vrev16.8
109 ;CHECK: vrev16.8
/external/llvm/test/CodeGen/ARM/
Dbig-endian-neon-extend.ll6 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
36 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
65 ; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
Dpopcnt.ll23 ; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
35 ; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
47 ; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
62 ; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
Dbig-endian-neon-trunc-store.ll18 ; CHECK: vrev16.8 [[REG]], [[REG]]
Dvrev.ll101 ;CHECK: vrev16.8
109 ;CHECK: vrev16.8
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvrev.ll101 ;CHECK: vrev16.8
109 ;CHECK: vrev16.8
/external/vixl/src/aarch32/
Dassembler-aarch32.h5509 void vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm);
5510 void vrev16(DataType dt, DRegister rd, DRegister rm) { in vrev16() function
5511 vrev16(al, dt, rd, rm); in vrev16()
5514 void vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm);
5515 void vrev16(DataType dt, QRegister rd, QRegister rm) { in vrev16() function
5516 vrev16(al, dt, rd, rm); in vrev16()
Ddisasm-aarch32.h2303 void vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm);
2305 void vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm);
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneont2.txt868 # CHECK: vrev16.8 d16, d16
870 # CHECK: vrev16.8 q8, q8
Dneon.txt977 # CHECK: vrev16.8 d16, d16
979 # CHECK: vrev16.8 q8, q8
/external/v8/src/arm/
Dassembler-arm.h1321 void vrev16(NeonSize size, QwNeonRegister dst, QwNeonRegister src);
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dneont2.txt868 # CHECK: vrev16.8 d16, d16
870 # CHECK: vrev16.8 q8, q8
Dneon.txt977 # CHECK: vrev16.8 d16, d16
979 # CHECK: vrev16.8 q8, q8
/external/llvm/test/MC/Disassembler/ARM/
Dneont2.txt868 # CHECK: vrev16.8 d16, d16
870 # CHECK: vrev16.8 q8, q8

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