Home
last modified time | relevance | path

Searched refs:vtst (Results 1 – 25 of 26) sorted by relevance

12

/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-cmp-encoding.s89 vtst.8 d16, d16, d17
90 vtst.16 d16, d16, d17
91 vtst.32 d16, d16, d17
92 vtst.8 q8, q8, q9
93 vtst.16 q8, q8, q9
94 vtst.32 q8, q8, q9
96 @ CHECK: vtst.8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf2]
97 @ CHECK: vtst.16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf2]
98 @ CHECK: vtst.32 d16, d16, d17 @ encoding: [0xb1,0x08,0x60,0xf2]
99 @ CHECK: vtst.8 q8, q8, q9 @ encoding: [0xf2,0x08,0x40,0xf2]
[all …]
/external/llvm/test/MC/ARM/
Dneon-cmp-encoding.s89 vtst.8 d16, d16, d17
90 vtst.16 d16, d16, d17
91 vtst.32 d16, d16, d17
92 vtst.8 q8, q8, q9
93 vtst.16 q8, q8, q9
94 vtst.32 q8, q8, q9
96 @ CHECK: vtst.8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf2]
97 @ CHECK: vtst.16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf2]
98 @ CHECK: vtst.32 d16, d16, d17 @ encoding: [0xb1,0x08,0x60,0xf2]
99 @ CHECK: vtst.8 q8, q8, q9 @ encoding: [0xf2,0x08,0x40,0xf2]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneon-cmp-encoding.s89 vtst.8 d16, d16, d17
90 vtst.16 d16, d16, d17
91 vtst.32 d16, d16, d17
92 vtst.8 q8, q8, q9
93 vtst.16 q8, q8, q9
94 vtst.32 q8, q8, q9
96 @ CHECK: vtst.8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf2]
97 @ CHECK: vtst.16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf2]
98 @ CHECK: vtst.32 d16, d16, d17 @ encoding: [0xb1,0x08,0x60,0xf2]
99 @ CHECK: vtst.8 q8, q8, q9 @ encoding: [0xf2,0x08,0x40,0xf2]
[all …]
/external/capstone/suite/MC/ARM/
Dneon-cmp-encoding.s.cs42 0xb1,0x08,0x40,0xf2 = vtst.8 d16, d16, d17
43 0xb1,0x08,0x50,0xf2 = vtst.16 d16, d16, d17
44 0xb1,0x08,0x60,0xf2 = vtst.32 d16, d16, d17
45 0xf2,0x08,0x40,0xf2 = vtst.8 q8, q8, q9
46 0xf2,0x08,0x50,0xf2 = vtst.16 q8, q8, q9
47 0xf2,0x08,0x60,0xf2 = vtst.32 q8, q8, q9
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvbits.ll445 ;CHECK: vtst.8
456 ;CHECK: vtst.16
467 ;CHECK: vtst.32
478 ;CHECK: vtst.8
489 ;CHECK: vtst.16
500 ;CHECK: vtst.32
/external/llvm/test/CodeGen/ARM/
Dvbits.ll445 ;CHECK: vtst.8
456 ;CHECK: vtst.16
467 ;CHECK: vtst.32
478 ;CHECK: vtst.8
489 ;CHECK: vtst.16
500 ;CHECK: vtst.32
/external/arm-neon-tests/
Dref_vtst.c35 #define INSN_NAME vtst
DMakefile.gcc56 vqdmlsl_n vsri_n vsli_n vtst vaddhn vraddhn vaddl vaddw \
DMakefile50 vqdmlsl_n vsri_n vsli_n vtst vaddhn vraddhn vaddl vaddw \
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvbits.ll705 ; CHECK-NEXT: vtst.8 d16, d17, d16
721 ; CHECK-NEXT: vtst.16 d16, d17, d16
737 ; CHECK-NEXT: vtst.32 d16, d17, d16
753 ; CHECK-NEXT: vtst.8 q8, q9, q8
770 ; CHECK-NEXT: vtst.16 q8, q9, q8
787 ; CHECK-NEXT: vtst.32 q8, q9, q8
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneon.txt416 # CHECK: vtst.8 d16, d16, d17
417 # CHECK: vtst.16 d16, d16, d17
418 # CHECK: vtst.32 d16, d16, d17
419 # CHECK: vtst.8 q8, q8, q9
420 # CHECK: vtst.16 q8, q8, q9
421 # CHECK: vtst.32 q8, q8, q9
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dneon.txt416 # CHECK: vtst.8 d16, d16, d17
417 # CHECK: vtst.16 d16, d16, d17
418 # CHECK: vtst.32 d16, d16, d17
419 # CHECK: vtst.8 q8, q8, q9
420 # CHECK: vtst.16 q8, q8, q9
421 # CHECK: vtst.32 q8, q8, q9
/external/llvm/test/MC/Disassembler/ARM/
Dneon.txt416 # CHECK: vtst.8 d16, d16, d17
417 # CHECK: vtst.16 d16, d16, d17
418 # CHECK: vtst.32 d16, d16, d17
419 # CHECK: vtst.8 q8, q8, q9
420 # CHECK: vtst.16 q8, q8, q9
421 # CHECK: vtst.32 q8, q8, q9
/external/clang/include/clang/Basic/
Darm_neon.td566 def VTST : WInst<"vtst", "udd", "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPs">;
1000 def CMTST : WInst<"vtst", "udd", "lUlPlQlQUlQPl">;
1522 def SCALAR_CMTST : SInst<"vtst", "sss", "SlSUl">;
/external/vixl/src/aarch32/
Dassembler-aarch32.h6115 void vtst(
6117 void vtst(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vtst() function
6118 vtst(al, dt, rd, rn, rm); in vtst()
6121 void vtst(
6123 void vtst(DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vtst() function
6124 vtst(al, dt, rd, rn, rm); in vtst()
Ddisasm-aarch32.h2611 void vtst(
2614 void vtst(
Ddisasm-aarch32.cc6911 void Disassembler::vtst( in vtst() function in vixl::aarch32::Disassembler
6922 void Disassembler::vtst( in vtst() function in vixl::aarch32::Disassembler
29867 vtst(CurrentCond(), in DecodeT32()
30619 vtst(CurrentCond(), in DecodeT32()
40096 vtst(al, dt, DRegister(rd), DRegister(rn), DRegister(rm)); in DecodeA32()
40142 vtst(al, dt, QRegister(rd), QRegister(rn), QRegister(rm)); in DecodeA32()
Dassembler-aarch32.cc27701 void Assembler::vtst( in vtst() function in vixl::aarch32::Assembler
27726 Delegate(kVtst, &Assembler::vtst, cond, dt, rd, rn, rm); in vtst()
27729 void Assembler::vtst( in vtst() function in vixl::aarch32::Assembler
27754 Delegate(kVtst, &Assembler::vtst, cond, dt, rd, rn, rm); in vtst()
Dmacro-assembler-aarch32.h10411 vtst(cond, dt, rd, rn, rm); in Vtst()
10426 vtst(cond, dt, rd, rn, rm); in Vtst()
/external/v8/src/arm/
Dassembler-arm.h1304 void vtst(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
Dassembler-arm.cc4715 void Assembler::vtst(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, in vtst() function in v8::internal::Assembler
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc7790 "vtst\005vudot\004vuzp\004vzip\003wfe\003wfi\005yield";
11610 …{ 2704 /* vtst */, ARM::VTSTv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, …
11611 …{ 2704 /* vtst */, ARM::VTSTv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, …
11612 …{ 2704 /* vtst */, ARM::VTSTv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, …
11613 …{ 2704 /* vtst */, ARM::VTSTv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, …
11614 …{ 2704 /* vtst */, ARM::VTSTv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, …
11615 …{ 2704 /* vtst */, ARM::VTSTv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON, {…
11616 …{ 2704 /* vtst */, ARM::VTSTv8i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, …
11617 …{ 2704 /* vtst */, ARM::VTSTv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, …
11618 …{ 2704 /* vtst */, ARM::VTSTv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasNEON, …
[all …]
/external/v8/src/compiler/arm/
Dcode-generator-arm.cc2643 __ vtst(Neon32, q_scratch, q_scratch, q_scratch); in AssembleArchInstruction() local
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td3715 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td4799 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;

12