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Searched refs:xtn2 (Results 1 – 25 of 41) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-convert-v4f64.ll9 ; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d
23 ; CHECK-DAG: xtn2 v[[NA2]].4s, v[[CONV3]].2d
25 ; CHECK-DAG: xtn2 v[[NA0]].4s, v[[CONV1]].2d
27 ; CHECK-DAG: xtn2 v[[TMP1]].8h, v[[NA0]].4s
49 ; CHECK: xtn2
61 ; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d
Dvcvt-oversize.ll11 ; CHECK-DAG: xtn2 v[[TMP]].8h, v[[MSB]].4s
Darm64-vmovn.ll33 ;CHECK: xtn2.16b v0, v1
43 ;CHECK: xtn2.8h v0, v1
53 ;CHECK: xtn2.4s v0, v1
Dconcat_vector-truncate-combine.ll35 ; CHECK-NEXT: xtn2.8h v0, v1
Dfp16-v8-instructions.ll401 ; CHECK-DAG: xtn2 [[I16]].8h, [[HIF32]]
415 ; CHECK-NEXT: xtn2 [[I16]].8h, [[HIF32]]
428 ; CHECK-DAG: xtn2 [[I16]].8h, [[HIF32]]
442 ; CHECK-NEXT: xtn2 [[I16]].8h, [[HIF32]]
/external/llvm/test/CodeGen/AArch64/
Darm64-convert-v4f64.ll9 ; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d
23 ; CHECK-DAG: xtn2 v[[NA2]].4s, v[[CONV3]].2d
25 ; CHECK-DAG: xtn2 v[[NA0]].4s, v[[CONV1]].2d
27 ; CHECK-DAG: xtn2 v[[TMP1]].8h, v[[NA0]].4s
49 ; CHECK: xtn2
61 ; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d
Dvcvt-oversize.ll11 ; CHECK-DAG: xtn2 v[[TMP]].8h, v[[MSB]].4s
Darm64-vmovn.ll33 ;CHECK: xtn2.16b v0, v1
43 ;CHECK: xtn2.8h v0, v1
53 ;CHECK: xtn2.4s v0, v1
Dconcat_vector-truncate-combine.ll35 ; CHECK-NEXT: xtn2.8h v0, v1
Dfp16-v8-instructions.ll377 ; CHECK-DAG: xtn2 [[I16]].8h, [[HIF32]]
391 ; CHECK-NEXT: xtn2 [[I16]].8h, [[HIF32]]
404 ; CHECK-DAG: xtn2 [[I16]].8h, [[HIF32]]
418 ; CHECK-NEXT: xtn2 [[I16]].8h, [[HIF32]]
/external/capstone/suite/MC/AArch64/
Dneon-simd-misc.s.cs104 0xe0,0x2b,0x21,0x4e = xtn2 v0.16b, v31.8h
105 0x82,0x28,0x61,0x4e = xtn2 v2.8h, v4.4s
106 0x06,0x29,0xa1,0x4e = xtn2 v6.4s, v8.2d
/external/libhevc/common/arm64/
Dihevc_sao_edge_offset_class1.s200 xtn2 v20.16b, v1.8h //vmovn_s16(pi2_tmp_cur_row.val[1])
213 xtn2 v30.16b, v28.8h //II vmovn_s16(pi2_tmp_cur_row.val[1])
246 xtn2 v30.16b, v28.8h //vmovn_s16(pi2_tmp_cur_row.val[1])
Dihevc_sao_edge_offset_class2.s353 xtn2 v20.16b, v22.8h //I vmovn_s16(pi2_tmp_cur_row.val[1])
456 xtn2 v26.16b, v28.8h //II vmovn_s16(pi2_tmp_cur_row.val[1])
467 xtn2 v20.16b, v18.8h //III vmovn_s16(pi2_tmp_cur_row.val[1])
527 xtn2 v20.16b, v5.8h //vmovn_s16(pi2_tmp_cur_row.val[1])
665 xtn2 v28.16b, v30.8h //vmovn_s16(pi2_tmp_cur_row.val[1])
Dihevc_sao_edge_offset_class3.s370 xtn2 v20.16b, v22.8h //I vmovn_s16(pi2_tmp_cur_row.val[1])
480 xtn2 v28.16b, v26.8h //II vmovn_s16(pi2_tmp_cur_row.val[1])
496 xtn2 v20.16b, v22.8h //III vmovn_s16(pi2_tmp_cur_row.val[1])
560 xtn2 v20.16b, v22.8h //vmovn_s16(pi2_tmp_cur_row.val[1])
703 xtn2 v28.16b, v30.8h //vmovn_s16(pi2_tmp_cur_row.val[1])
Dihevc_sao_edge_offset_class1_chroma.s246 xtn2 v20.16b, v28.8h //vmovn_s16(pi2_tmp_cur_row.val[1])
261 xtn2 v30.16b, v28.8h //II vmovn_s16(pi2_tmp_cur_row.val[1])
306 xtn2 v30.16b, v28.8h //vmovn_s16(pi2_tmp_cur_row.val[1])
Dihevc_sao_edge_offset_class3_chroma.s488 xtn2 v20.16b, v18.8h //I vmovn_s16(pi2_tmp_cur_row.val[1])
642 xtn2 v28.16b, v26.8h //II vmovn_s16(pi2_tmp_cur_row.val[1])
661 xtn2 v20.16b, v18.8h //III vmovn_s16(pi2_tmp_cur_row.val[1])
746 xtn2 v20.16b, v18.8h //III vmovn_s16(pi2_tmp_cur_row.val[1])
930 xtn2 v28.16b, v30.8h //vmovn_s16(pi2_tmp_cur_row.val[1])
Dihevc_sao_edge_offset_class2_chroma.s510 xtn2 v20.16b, v18.8h //I vmovn_s16(pi2_tmp_cur_row.val[1])
650 xtn2 v28.16b, v26.8h //II vmovn_s16(pi2_tmp_cur_row.val[1])
679 xtn2 v20.16b, v18.8h //III vmovn_s16(pi2_tmp_cur_row.val[1])
755 xtn2 v20.16b, v18.8h //vmovn_s16(pi2_tmp_cur_row.val[1])
917 xtn2 v28.16b, v26.8h //vmovn_s16(pi2_tmp_cur_row.val[1])
/external/llvm/test/MC/AArch64/
Dneon-simd-misc.s333 xtn2 v0.16b, v31.8h
334 xtn2 v2.8h, v4.4s
335 xtn2 v6.4s, v8.2d
Darm64-advsimd.s2052 xtn2 v14.16b, v14.8h
2054 xtn2 v14.8h, v14.4s
2056 xtn2 v14.4s, v14.2d
2058 ; CHECK: xtn2.16b v14, v14 ; encoding: [0xce,0x29,0x21,0x4e]
2060 ; CHECK: xtn2.8h v14, v14 ; encoding: [0xce,0x29,0x61,0x4e]
2062 ; CHECK: xtn2.4s v14, v14 ; encoding: [0xce,0x29,0xa1,0x4e]
Dneon-diagnostics.s5636 xtn2 v1.8b, v9.8h
5637 xtn2 v13.4h, v21.4s
5638 xtn2 v4.2s, v0.2d
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-simd-misc.s333 xtn2 v0.16b, v31.8h
334 xtn2 v2.8h, v4.4s
335 xtn2 v6.4s, v8.2d
Darm64-advsimd.s2052 xtn2 v14.16b, v14.8h
2054 xtn2 v14.8h, v14.4s
2056 xtn2 v14.4s, v14.2d
2058 ; CHECK: xtn2.16b v14, v14 ; encoding: [0xce,0x29,0x21,0x4e]
2060 ; CHECK: xtn2.8h v14, v14 ; encoding: [0xce,0x29,0x61,0x4e]
2062 ; CHECK: xtn2.4s v14, v14 ; encoding: [0xce,0x29,0xa1,0x4e]
Dneon-diagnostics.s5576 xtn2 v1.8b, v9.8h
5577 xtn2 v13.4h, v21.4s
5578 xtn2 v4.2s, v0.2d
/external/libavc/common/armv8/
Dih264_iquant_itrans_recon_av8.s700 xtn2 v1.8h, v23.4s
702 xtn2 v3.8h, v29.4s
704 xtn2 v5.8h, v27.4s
706 xtn2 v7.8h, v25.4s
/external/libjpeg-turbo/simd/arm64/
Djsimd_neon.S3262 xtn2 v16.16b, v17.8h
3264 xtn2 v18.16b, v19.8h
3266 xtn2 v20.16b, v21.8h
3270 xtn2 v22.16b, v17.8h

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