1 /** 2 * Copyright (c) 2014, AppliedMicro Corp. All rights reserved. 3 * Copyright (c) 2016, Hisilicon Limited. All rights reserved. 4 * Copyright (c) 2016, Linaro Limited. All rights reserved. 5 * 6 * This program and the accompanying materials 7 * are licensed and made available under the terms and conditions of the BSD License 8 * which accompanies this distribution. The full text of the license may be found at 9 * http://opensource.org/licenses/bsd-license.php 10 * 11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 * 14 **/ 15 16 #ifndef _PCI_HOST_BRIDGE_H_ 17 #define _PCI_HOST_BRIDGE_H_ 18 19 #include <PiDxe.h> 20 21 #include <IndustryStandard/Pci.h> 22 #include <IndustryStandard/Acpi.h> 23 24 #include <Protocol/PciHostBridgeResourceAllocation.h> 25 #include <Protocol/PciRootBridgeIo.h> 26 #include <Protocol/Metronome.h> 27 #include <Protocol/DevicePath.h> 28 #include <Protocol/PciIo.h> 29 #include <Protocol/CpuIo2.h> 30 31 32 #include <Library/BaseLib.h> 33 #include <Library/DebugLib.h> 34 #include <Library/BaseMemoryLib.h> 35 #include <Library/MemoryAllocationLib.h> 36 #include <Library/UefiLib.h> 37 #include <Library/UefiBootServicesTableLib.h> 38 #include <Library/DxeServicesTableLib.h> 39 #include <Library/DevicePathLib.h> 40 #include <Library/IoLib.h> 41 #include <Library/PciLib.h> 42 #include <Library/PcdLib.h> 43 #include <Library/PlatformPciLib.h> 44 45 // Enable below statments to enable PCIE debug 46 //#define PCIE_DEBUG_ENABLE 47 //#define PCIE_VDEBUG_ENABLE 48 //#define PCIE_CDEBUG_ENABLE 49 50 #ifdef PCIE_CDEBUG_ENABLE 51 # define PCIE_CSR_DEBUG(arg...) DEBUG((EFI_D_VERBOSE,## arg)) 52 #else 53 # define PCIE_CSR_DEBUG(arg...) 54 #endif 55 56 #ifdef PCIE_VDEBUG_ENABLE 57 # define PCIE_VDEBUG(arg...) DEBUG((EFI_D_VERBOSE,## arg)) 58 #else 59 # define PCIE_VDEBUG(arg...) 60 #endif 61 62 #ifdef PCIE_DEBUG_ENABLE 63 # define PCIE_DEBUG(arg...) DEBUG((EFI_D_VERBOSE,## arg)) 64 #else 65 # define PCIE_DEBUG(arg...) 66 #endif 67 #define PCIE_WARN(arg...) DEBUG((EFI_D_WARN,## arg)) 68 #define PCIE_ERR(arg...) DEBUG((EFI_D_ERROR,## arg)) 69 #define PCIE_INFO(arg...) DEBUG((EFI_D_INFO,## arg)) 70 71 #define MAX_PCI_DEVICE_NUMBER 31 72 #define MAX_PCI_FUNCTION_NUMBER 7 73 #define MAX_PCI_REG_ADDRESS 0xFFFF 74 75 typedef enum { 76 IoOperation, 77 MemOperation, 78 PciOperation 79 } OPERATION_TYPE; 80 81 #define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't') 82 typedef struct { 83 UINTN Signature; 84 EFI_HANDLE HostBridgeHandle; 85 UINTN RootBridgeNumber; 86 LIST_ENTRY Head; 87 BOOLEAN ResourceSubmited; 88 BOOLEAN CanRestarted; 89 EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc; 90 } PCI_HOST_BRIDGE_INSTANCE; 91 92 #define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \ 93 CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE) 94 95 // 96 // HostBridge Resource Allocation interface 97 // 98 99 /** 100 These are the notifications from the PCI bus driver that it is about to enter a certain 101 phase of the PCI enumeration process. 102 103 This member function can be used to notify the host bridge driver to perform specific actions, 104 including any chipset-specific initialization, so that the chipset is ready to enter the next phase. 105 Eight notification points are defined at this time. See belows: 106 EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data 107 structures. The PCI enumerator should issue this notification 108 before starting a fresh enumeration process. Enumeration cannot 109 be restarted after sending any other notification such as 110 EfiPciHostBridgeBeginBusAllocation. 111 EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is 112 required here. This notification can be used to perform any 113 chipset-specific programming. 114 EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No 115 specific action is required here. This notification can be used to 116 perform any chipset-specific programming. 117 EfiPciHostBridgeBeginResourceAllocation 118 The resource allocation phase is about to begin. No specific 119 action is required here. This notification can be used to perform 120 any chipset-specific programming. 121 EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI 122 root bridges. These resource settings are returned on the next call to 123 GetProposedResources(). Before calling NotifyPhase() with a Phase of 124 EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible 125 for gathering I/O and memory requests for 126 all the PCI root bridges and submitting these requests using 127 SubmitResources(). This function pads the resource amount 128 to suit the root bridge hardware, takes care of dependencies between 129 the PCI root bridges, and calls the Global Coherency Domain (GCD) 130 with the allocation request. In the case of padding, the allocated range 131 could be bigger than what was requested. 132 EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated 133 resources (proposed resources) for all the PCI root bridges. After the 134 hardware is programmed, reassigning resources will not be supported. 135 The bus settings are not affected. 136 EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI 137 root bridges and resets the I/O and memory apertures to their initial 138 state. The bus settings are not affected. If the request to allocate 139 resources fails, the PCI enumerator can use this notification to 140 deallocate previous resources, adjust the requests, and retry 141 allocation. 142 EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is 143 required here. This notification can be used to perform any chipsetspecific 144 programming. 145 146 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL 147 @param[in] Phase The phase during enumeration 148 149 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error 150 is valid for a Phase of EfiPciHostBridgeAllocateResources if 151 SubmitResources() has not been called for one or more 152 PCI root bridges before this call 153 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid 154 for a Phase of EfiPciHostBridgeSetResources. 155 @retval EFI_INVALID_PARAMETER Invalid phase parameter 156 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 157 This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the 158 previously submitted resource requests cannot be fulfilled or 159 were only partially fulfilled. 160 @retval EFI_SUCCESS The notification was accepted without any errors. 161 162 **/ 163 EFI_STATUS 164 EFIAPI 165 NotifyPhase( 166 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, 167 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase 168 ); 169 170 /** 171 Return the device handle of the next PCI root bridge that is associated with this Host Bridge. 172 173 This function is called multiple times to retrieve the device handles of all the PCI root bridges that 174 are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI 175 root bridges. On each call, the handle that was returned by the previous call is passed into the 176 interface, and on output the interface returns the device handle of the next PCI root bridge. The 177 caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL 178 for that root bridge. When there are no more PCI root bridges to report, the interface returns 179 EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they 180 are returned by this function. 181 For D945 implementation, there is only one root bridge in PCI host bridge. 182 183 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL 184 @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge. 185 186 @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the 187 specific Host bridge and return EFI_SUCCESS. 188 @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge. 189 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was 190 returned on a previous call to GetNextRootBridge(). 191 **/ 192 EFI_STATUS 193 EFIAPI 194 GetNextRootBridge( 195 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, 196 IN OUT EFI_HANDLE *RootBridgeHandle 197 ); 198 199 /** 200 Returns the allocation attributes of a PCI root bridge. 201 202 The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary 203 from one PCI root bridge to another. These attributes are different from the decode-related 204 attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The 205 RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device 206 handles of all the root bridges that are associated with this host bridge must be obtained by calling 207 GetNextRootBridge(). The attributes are static in the sense that they do not change during or 208 after the enumeration process. The hardware may provide mechanisms to change the attributes on 209 the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is 210 installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in 211 "Related Definitions" below. The caller uses these attributes to combine multiple resource requests. 212 For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to 213 include requests for the prefetchable memory in the nonprefetchable memory pool and not request any 214 prefetchable memory. 215 Attribute Description 216 ------------------------------------ ---------------------------------------------------------------------- 217 EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate 218 windows for nonprefetchable and prefetchable memory. A PCI bus 219 driver needs to include requests for prefetchable memory in the 220 nonprefetchable memory pool. 221 222 EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory 223 windows. If this bit is not set, the PCI bus driver needs to include 224 requests for a 64-bit memory address in the corresponding 32-bit 225 memory pool. 226 227 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL 228 @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type 229 EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification. 230 @param[out] Attributes The pointer to attribte of root bridge, it is output parameter 231 232 @retval EFI_INVALID_PARAMETER Attribute pointer is NULL 233 @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid. 234 @retval EFI_SUCCESS Success to get attribute of interested root bridge. 235 236 **/ 237 EFI_STATUS 238 EFIAPI 239 GetAttributes( 240 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, 241 IN EFI_HANDLE RootBridgeHandle, 242 OUT UINT64 *Attributes 243 ); 244 245 /** 246 Sets up the specified PCI root bridge for the bus enumeration process. 247 248 This member function sets up the root bridge for bus enumeration and returns the PCI bus range 249 over which the search should be performed in ACPI 2.0 resource descriptor format. 250 251 @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance. 252 @param[in] RootBridgeHandle The PCI Root Bridge to be set up. 253 @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor. 254 255 @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle 256 @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag. 257 @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor. 258 259 **/ 260 EFI_STATUS 261 EFIAPI 262 StartBusEnumeration( 263 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, 264 IN EFI_HANDLE RootBridgeHandle, 265 OUT VOID **Configuration 266 ); 267 268 /** 269 Programs the PCI root bridge hardware so that it decodes the specified PCI bus range. 270 271 This member function programs the specified PCI root bridge to decode the bus range that is 272 specified by the input parameter Configuration. 273 The bus range information is specified in terms of the ACPI 2.0 resource descriptor format. 274 275 @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance 276 @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed 277 @param[in] Configuration The pointer to the PCI bus resource descriptor 278 279 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. 280 @retval EFI_INVALID_PARAMETER Configuration is NULL. 281 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor. 282 @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor. 283 @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than 284 bus descriptors. 285 @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors. 286 @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge. 287 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge. 288 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. 289 @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed. 290 291 **/ 292 EFI_STATUS 293 EFIAPI 294 SetBusNumbers( 295 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, 296 IN EFI_HANDLE RootBridgeHandle, 297 IN VOID *Configuration 298 ); 299 300 /** 301 Submits the I/O and memory resource requirements for the specified PCI root bridge. 302 303 This function is used to submit all the I/O and memory resources that are required by the specified 304 PCI root bridge. The input parameter Configuration is used to specify the following: 305 - The various types of resources that are required 306 - The associated lengths in terms of ACPI 2.0 resource descriptor format 307 308 @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance. 309 @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted. 310 @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor. 311 312 @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted. 313 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. 314 @retval EFI_INVALID_PARAMETER Configuration is NULL. 315 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor. 316 @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are 317 not supported by this PCI root bridge. This error will happen if the caller 318 did not combine resources according to Attributes that were returned by 319 GetAllocAttributes(). 320 @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid. 321 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge. 322 @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge. 323 324 **/ 325 EFI_STATUS 326 EFIAPI 327 SubmitResources( 328 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, 329 IN EFI_HANDLE RootBridgeHandle, 330 IN VOID *Configuration 331 ); 332 333 /** 334 Returns the proposed resource settings for the specified PCI root bridge. 335 336 This member function returns the proposed resource settings for the specified PCI root bridge. The 337 proposed resource settings are prepared when NotifyPhase() is called with a Phase of 338 EfiPciHostBridgeAllocateResources. The output parameter Configuration 339 specifies the following: 340 - The various types of resources, excluding bus resources, that are allocated 341 - The associated lengths in terms of ACPI 2.0 resource descriptor format 342 343 @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance. 344 @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification. 345 @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor. 346 347 @retval EFI_SUCCESS The requested parameters were returned. 348 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. 349 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. 350 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 351 352 **/ 353 EFI_STATUS 354 EFIAPI 355 GetProposedResources( 356 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, 357 IN EFI_HANDLE RootBridgeHandle, 358 OUT VOID **Configuration 359 ); 360 361 /** 362 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various 363 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual 364 PCI controllers before enumeration. 365 366 This function is called during the PCI enumeration process. No specific action is expected from this 367 member function. It allows the host bridge driver to preinitialize individual PCI controllers before 368 enumeration. 369 370 @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance. 371 @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in 372 InstallProtocolInterface() in the UEFI 2.0 Specification. 373 @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the 374 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI 375 configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for 376 the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS. 377 @param Phase The phase of the PCI device enumeration. 378 379 @retval EFI_SUCCESS The requested parameters were returned. 380 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle. 381 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in 382 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE. 383 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should 384 not enumerate this device, including its child devices if it is a PCI-to-PCI 385 bridge. 386 387 **/ 388 EFI_STATUS 389 EFIAPI 390 PreprocessController ( 391 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, 392 IN EFI_HANDLE RootBridgeHandle, 393 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, 394 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase 395 ); 396 397 398 // 399 // Define resource status constant 400 // 401 #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL 402 #define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL 403 404 405 // 406 // Driver Instance Data Prototypes 407 // 408 409 typedef struct { 410 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation; 411 UINTN NumberOfBytes; 412 UINTN NumberOfPages; 413 EFI_PHYSICAL_ADDRESS HostAddress; 414 EFI_PHYSICAL_ADDRESS MappedHostAddress; 415 } MAP_INFO; 416 417 typedef struct { 418 ACPI_HID_DEVICE_PATH AcpiDevicePath; 419 EFI_DEVICE_PATH_PROTOCOL EndDevicePath; 420 } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; 421 422 typedef enum { 423 TypeIo = 0, 424 TypeMem32, 425 TypePMem32, 426 TypeMem64, 427 TypePMem64, 428 TypeBus, 429 TypeMax 430 } PCI_RESOURCE_TYPE; 431 432 typedef enum { 433 ResNone = 0, 434 ResSubmitted, 435 ResRequested, 436 ResAllocated, 437 ResStatusMax 438 } RES_STATUS; 439 440 typedef struct { 441 PCI_RESOURCE_TYPE Type; 442 UINT64 Base; 443 UINT64 Length; 444 UINT64 Alignment; 445 RES_STATUS Status; 446 } PCI_RES_NODE; 447 448 #define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('e', '2', 'p', 'b') 449 450 typedef struct { 451 UINT32 Signature; 452 LIST_ENTRY Link; 453 EFI_HANDLE Handle; 454 UINT64 RootBridgeAttrib; 455 UINT64 Attributes; 456 UINT64 Supports; 457 458 // 459 // Specific for this memory controller: Bus, I/O, Mem 460 // 461 PCI_RES_NODE ResAllocNode[6]; 462 463 // 464 // Addressing for Memory and I/O and Bus arrange 465 // 466 UINT64 BusBase; 467 UINT64 MemBase; 468 UINT64 IoBase; 469 UINT64 BusLimit; 470 UINT64 MemLimit; 471 UINT64 IoLimit; 472 UINT64 RbPciBar; 473 UINT64 Ecam; 474 475 UINTN PciAddress; 476 UINTN PciData; 477 UINTN Port; 478 UINT32 SocType; 479 UINT64 CpuMemRegionBase; 480 UINT64 CpuIoRegionBase; 481 UINT64 PciRegionBase; 482 UINT64 PciRegionLimit; 483 484 EFI_DEVICE_PATH_PROTOCOL *DevicePath; 485 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; 486 487 } PCI_ROOT_BRIDGE_INSTANCE; 488 489 490 // 491 // Driver Instance Data Macros 492 // 493 #define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \ 494 CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE) 495 496 497 #define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \ 498 CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE) 499 500 /** 501 502 Construct the Pci Root Bridge Io protocol 503 504 @param Protocol Point to protocol instance 505 @param HostBridgeHandle Handle of host bridge 506 @param Attri Attribute of host bridge 507 @param ResAppeture ResourceAppeture for host bridge 508 509 @retval EFI_SUCCESS Success to initialize the Pci Root Bridge. 510 511 **/ 512 EFI_STATUS 513 RootBridgeConstructor ( 514 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol, 515 IN EFI_HANDLE HostBridgeHandle, 516 IN UINT64 Attri, 517 IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture, 518 IN UINT32 Seg 519 ); 520 521 #endif 522