1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the Mips Disassembler.
11 //
12 //===----------------------------------------------------------------------===//
13
14 /* Capstone Disassembly Engine */
15 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
16
17 #ifdef CAPSTONE_HAS_MIPS
18
19 #include <stdio.h>
20 #include <string.h>
21
22 #include <platform.h>
23
24 #include "../../utils.h"
25
26 #include "../../MCInst.h"
27 #include "../../MCRegisterInfo.h"
28 #include "../../SStream.h"
29
30 #include "../../MathExtras.h"
31
32 //#include "Mips.h"
33 //#include "MipsRegisterInfo.h"
34 //#include "MipsSubtarget.h"
35 #include "../../MCFixedLenDisassembler.h"
36 #include "../../MCInst.h"
37 //#include "llvm/MC/MCSubtargetInfo.h"
38 #include "../../MCRegisterInfo.h"
39 #include "../../MCDisassembler.h"
40
41 // Forward declare these because the autogenerated code will reference them.
42 // Definitions are further down.
43 static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
44 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
45
46 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
47 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
48
49 static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
50 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
51
52 static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
53 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
54
55 static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst,
56 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
57
58 static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
59 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
60
61 static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
62 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
63
64 static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
65 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
66
67 static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
68 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
69
70 static DecodeStatus DecodeCCRegisterClass(MCInst *Inst,
71 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
72
73 static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst,
74 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
75
76 static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst,
77 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
78
79 static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
80 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
81
82 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst,
83 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
84
85 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
86 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
87
88 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
89 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
90
91 static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst,
92 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
93
94 static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst,
95 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
96
97 static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
98 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
99
100 static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
101 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
102
103 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
104 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
105
106 static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
107 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
108
109 static DecodeStatus DecodeBranchTarget(MCInst *Inst,
110 unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
111
112 static DecodeStatus DecodeJumpTarget(MCInst *Inst,
113 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
114
115 static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
116 unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
117
118 static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
119 unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
120
121 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
122 // shifted left by 1 bit.
123 static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
124 unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
125
126 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
127 // shifted left by 1 bit.
128 static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
129 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
130
131 static DecodeStatus DecodeMem(MCInst *Inst,
132 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
133
134 static DecodeStatus DecodeCachePref(MCInst *Inst,
135 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
136
137 static DecodeStatus DecodeMSA128Mem(MCInst *Inst,
138 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
139
140 static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
141 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
142
143 static DecodeStatus DecodeMemMMImm16(MCInst *Inst,
144 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
145
146 static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn,
147 uint64_t Address, MCRegisterInfo *Decoder);
148
149 static DecodeStatus DecodeCOP2Mem(MCInst *Inst, unsigned Insn,
150 uint64_t Address, MCRegisterInfo *Decoder);
151
152 static DecodeStatus DecodeCOP3Mem(MCInst *Inst, unsigned Insn,
153 uint64_t Address, MCRegisterInfo *Decoder);
154
155 static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
156 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
157
158 static DecodeStatus DecodeSimm16(MCInst *Inst,
159 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
160
161 // Decode the immediate field of an LSA instruction which
162 // is off by one.
163 static DecodeStatus DecodeLSAImm(MCInst *Inst,
164 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
165
166 static DecodeStatus DecodeInsSize(MCInst *Inst,
167 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
168
169 static DecodeStatus DecodeExtSize(MCInst *Inst,
170 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
171
172 static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
173 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
174
175 static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
176 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
177
178 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
179 /// handle.
180 static DecodeStatus DecodeINSVE_DF_4(MCInst *MI,
181 uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
182
183 static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI,
184 uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
185
186 static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI,
187 uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
188
189 static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI,
190 uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
191
192 static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI,
193 uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
194
195 static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI,
196 uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
197
198 static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI,
199 uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
200
201
202 #define GET_SUBTARGETINFO_ENUM
203 #include "MipsGenSubtargetInfo.inc"
204
205 // Hacky: enable all features for disassembler
getFeatureBits(int mode)206 static uint64_t getFeatureBits(int mode)
207 {
208 uint64_t Bits = (uint64_t)-1; // include every features at first
209
210 // By default we do not support Mips1
211 Bits &= ~Mips_FeatureMips1;
212
213 // No MicroMips
214 Bits &= ~Mips_FeatureMicroMips;
215
216 // ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate()
217 // some features are mutually execlusive
218 if (mode & CS_MODE_16) {
219 //Bits &= ~Mips_FeatureMips32r2;
220 //Bits &= ~Mips_FeatureMips32;
221 //Bits &= ~Mips_FeatureFPIdx;
222 //Bits &= ~Mips_FeatureBitCount;
223 //Bits &= ~Mips_FeatureSwap;
224 //Bits &= ~Mips_FeatureSEInReg;
225 //Bits &= ~Mips_FeatureMips64r2;
226 //Bits &= ~Mips_FeatureFP64Bit;
227 } else if (mode & CS_MODE_32) {
228 Bits &= ~Mips_FeatureMips16;
229 Bits &= ~Mips_FeatureFP64Bit;
230 Bits &= ~Mips_FeatureMips64r2;
231 Bits &= ~Mips_FeatureMips32r6;
232 Bits &= ~Mips_FeatureMips64r6;
233 } else if (mode & CS_MODE_64) {
234 Bits &= ~Mips_FeatureMips16;
235 Bits &= ~Mips_FeatureMips64r6;
236 Bits &= ~Mips_FeatureMips32r6;
237 } else if (mode & CS_MODE_MIPS32R6) {
238 Bits |= Mips_FeatureMips32r6;
239 Bits &= ~Mips_FeatureMips16;
240 Bits &= ~Mips_FeatureFP64Bit;
241 Bits &= ~Mips_FeatureMips64r6;
242 Bits &= ~Mips_FeatureMips64r2;
243 }
244
245 if (mode & CS_MODE_MICRO) {
246 Bits |= Mips_FeatureMicroMips;
247 Bits &= ~Mips_FeatureMips4_32r2;
248 Bits &= ~Mips_FeatureMips2;
249 }
250
251 return Bits;
252 }
253
254 #include "MipsGenDisassemblerTables.inc"
255
256 #define GET_REGINFO_ENUM
257 #include "MipsGenRegisterInfo.inc"
258
259 #define GET_REGINFO_MC_DESC
260 #include "MipsGenRegisterInfo.inc"
261
262 #define GET_INSTRINFO_ENUM
263 #include "MipsGenInstrInfo.inc"
264
Mips_init(MCRegisterInfo * MRI)265 void Mips_init(MCRegisterInfo *MRI)
266 {
267 // InitMCRegisterInfo(MipsRegDesc, 394, RA, PC,
268 // MipsMCRegisterClasses, 48,
269 // MipsRegUnitRoots,
270 // 273,
271 // MipsRegDiffLists,
272 // MipsRegStrings,
273 // MipsSubRegIdxLists,
274 // 12,
275 // MipsSubRegIdxRanges,
276 // MipsRegEncodingTable);
277
278 MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 394,
279 0, 0,
280 MipsMCRegisterClasses, 48,
281 0, 0,
282 MipsRegDiffLists,
283 0,
284 MipsSubRegIdxLists, 12,
285 0);
286 }
287
288 /// readInstruction - read four bytes from the MemoryObject
289 /// and return 32 bit word sorted according to the given endianess
readInstruction32(unsigned char * code,uint32_t * insn,bool isBigEndian,bool isMicroMips)290 static DecodeStatus readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips)
291 {
292 // We want to read exactly 4 Bytes of data.
293 if (isBigEndian) {
294 // Encoded as a big-endian 32-bit word in the stream.
295 *insn = (code[3] << 0) |
296 (code[2] << 8) |
297 (code[1] << 16) |
298 (code[0] << 24);
299 } else {
300 // Encoded as a small-endian 32-bit word in the stream.
301 // Little-endian byte ordering:
302 // mips32r2: 4 | 3 | 2 | 1
303 // microMIPS: 2 | 1 | 4 | 3
304 if (isMicroMips) {
305 *insn = (code[2] << 0) |
306 (code[3] << 8) |
307 (code[0] << 16) |
308 (code[1] << 24);
309 } else {
310 *insn = (code[0] << 0) |
311 (code[1] << 8) |
312 (code[2] << 16) |
313 (code[3] << 24);
314 }
315 }
316
317 return MCDisassembler_Success;
318 }
319
MipsDisassembler_getInstruction(int mode,MCInst * instr,const uint8_t * code,size_t code_len,uint16_t * Size,uint64_t Address,bool isBigEndian,MCRegisterInfo * MRI)320 static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
321 const uint8_t *code, size_t code_len,
322 uint16_t *Size,
323 uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI)
324 {
325 uint32_t Insn;
326 DecodeStatus Result;
327
328 if (code_len < 4)
329 // not enough data
330 return MCDisassembler_Fail;
331
332 if (instr->flat_insn->detail) {
333 memset(instr->flat_insn->detail, 0, sizeof(cs_detail));
334 }
335
336 Result = readInstruction32((unsigned char*)code, &Insn, isBigEndian,
337 mode & CS_MODE_MICRO);
338 if (Result == MCDisassembler_Fail)
339 return MCDisassembler_Fail;
340
341 if (mode & CS_MODE_MICRO) {
342 // Calling the auto-generated decoder function.
343 Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, MRI, mode);
344 if (Result != MCDisassembler_Fail) {
345 *Size = 4;
346 return Result;
347 }
348 return MCDisassembler_Fail;
349 }
350
351 #if 0
352 // TODO: properly handle this in the future with MIPS1/2 modes
353 if (((mode & CS_MODE_32) == 0) && ((mode & CS_MODE_MIPS3) == 0)) { // COP3
354 // DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
355 Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode);
356 if (Result != MCDisassembler_Fail) {
357 *Size = 4;
358 return Result;
359 }
360 }
361 #endif
362
363 if (((mode & CS_MODE_MIPS32R6) != 0) && ((mode & CS_MODE_MIPSGP64) != 0)) {
364 // DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
365 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
366 Address, MRI, mode);
367 if (Result != MCDisassembler_Fail) {
368 *Size = 4;
369 return Result;
370 }
371 }
372
373 if ((mode & CS_MODE_MIPS32R6) != 0) {
374 // DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
375 Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
376 Address, MRI, mode);
377 if (Result != MCDisassembler_Fail) {
378 *Size = 4;
379 return Result;
380 }
381 }
382
383 // Calling the auto-generated decoder function.
384 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode);
385 if (Result != MCDisassembler_Fail) {
386 *Size = 4;
387 return Result;
388 }
389
390 return MCDisassembler_Fail;
391 }
392
Mips_getInstruction(csh ud,const uint8_t * code,size_t code_len,MCInst * instr,uint16_t * size,uint64_t address,void * info)393 bool Mips_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr,
394 uint16_t *size, uint64_t address, void *info)
395 {
396 cs_struct *handle = (cs_struct *)(uintptr_t)ud;
397
398 DecodeStatus status = MipsDisassembler_getInstruction(handle->mode, instr,
399 code, code_len,
400 size,
401 address, handle->big_endian, (MCRegisterInfo *)info);
402
403 return status == MCDisassembler_Success;
404 }
405
Mips64Disassembler_getInstruction(int mode,MCInst * instr,const uint8_t * code,size_t code_len,uint16_t * Size,uint64_t Address,bool isBigEndian,MCRegisterInfo * MRI)406 static DecodeStatus Mips64Disassembler_getInstruction(int mode, MCInst *instr,
407 const uint8_t *code, size_t code_len,
408 uint16_t *Size,
409 uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI)
410 {
411 uint32_t Insn;
412 DecodeStatus Result;
413
414 if (code_len < 4)
415 // not enough data
416 return MCDisassembler_Fail;
417
418 if (instr->flat_insn->detail) {
419 memset(instr->flat_insn->detail, 0, sizeof(cs_detail));
420 }
421
422 Result = readInstruction32((unsigned char*)code, &Insn, isBigEndian, false);
423 if (Result == MCDisassembler_Fail)
424 return MCDisassembler_Fail;
425
426 if (instr->flat_insn->detail) {
427 memset(instr->flat_insn->detail, 0, sizeof(cs_detail));
428 }
429
430 // Calling the auto-generated decoder function.
431 Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address, MRI, mode);
432 if (Result != MCDisassembler_Fail) {
433 *Size = 4;
434 return Result;
435 }
436
437 // If we fail to decode in Mips64 decoder space we can try in Mips32
438 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode);
439 if (Result != MCDisassembler_Fail) {
440 *Size = 4;
441 return Result;
442 }
443
444 return MCDisassembler_Fail;
445 }
446
Mips64_getInstruction(csh ud,const uint8_t * code,size_t code_len,MCInst * instr,uint16_t * size,uint64_t address,void * info)447 bool Mips64_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr,
448 uint16_t *size, uint64_t address, void *info)
449 {
450 cs_struct *handle = (cs_struct *)(uintptr_t)ud;
451
452 DecodeStatus status = Mips64Disassembler_getInstruction(handle->mode, instr,
453 code, code_len,
454 size,
455 address, handle->big_endian, (MCRegisterInfo *)info);
456
457 return status == MCDisassembler_Success;
458 }
459
getReg(MCRegisterInfo * MRI,unsigned RC,unsigned RegNo)460 static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
461 {
462 //MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
463 //return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
464 MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
465 return rc->RegsBegin[RegNo];
466 }
467
DecodeINSVE_DF_4(MCInst * MI,uint32_t insn,uint64_t Address,MCRegisterInfo * Decoder)468 static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn,
469 uint64_t Address, MCRegisterInfo *Decoder)
470 {
471 typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, MCRegisterInfo *);
472 // The size of the n field depends on the element size
473 // The register class also depends on this.
474 uint32_t tmp = fieldFromInstruction(insn, 17, 5);
475 unsigned NSize = 0;
476 DecodeFN RegDecoder = NULL;
477
478 if ((tmp & 0x18) == 0x00) { // INSVE_B
479 NSize = 4;
480 RegDecoder = DecodeMSA128BRegisterClass;
481 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
482 NSize = 3;
483 RegDecoder = DecodeMSA128HRegisterClass;
484 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
485 NSize = 2;
486 RegDecoder = DecodeMSA128WRegisterClass;
487 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
488 NSize = 1;
489 RegDecoder = DecodeMSA128DRegisterClass;
490 } //else llvm_unreachable("Invalid encoding");
491
492 //assert(NSize != 0 && RegDecoder != nullptr);
493 if (NSize == 0 || RegDecoder == NULL)
494 return MCDisassembler_Fail;
495
496 if (RegDecoder == NULL)
497 return MCDisassembler_Fail;
498
499 // $wd
500 tmp = fieldFromInstruction(insn, 6, 5);
501 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail)
502 return MCDisassembler_Fail;
503
504 // $wd_in
505 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail)
506 return MCDisassembler_Fail;
507
508 // $n
509 tmp = fieldFromInstruction(insn, 16, NSize);
510 MCOperand_CreateImm0(MI, tmp);
511
512 // $ws
513 tmp = fieldFromInstruction(insn, 11, 5);
514 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail)
515 return MCDisassembler_Fail;
516
517 // $n2
518 MCOperand_CreateImm0(MI, 0);
519
520 return MCDisassembler_Success;
521 }
522
DecodeAddiGroupBranch_4(MCInst * MI,uint32_t insn,uint64_t Address,MCRegisterInfo * Decoder)523 static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn,
524 uint64_t Address, MCRegisterInfo *Decoder)
525 {
526 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
527 // (otherwise we would have matched the ADDI instruction from the earlier
528 // ISA's instead).
529 //
530 // We have:
531 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
532 // BOVC if rs >= rt
533 // BEQZALC if rs == 0 && rt != 0
534 // BEQC if rs < rt && rs != 0
535
536 uint32_t Rs = fieldFromInstruction(insn, 21, 5);
537 uint32_t Rt = fieldFromInstruction(insn, 16, 5);
538 uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
539 bool HasRs = false;
540
541 if (Rs >= Rt) {
542 MCInst_setOpcode(MI, Mips_BOVC);
543 HasRs = true;
544 } else if (Rs != 0 && Rs < Rt) {
545 MCInst_setOpcode(MI, Mips_BEQC);
546 HasRs = true;
547 } else
548 MCInst_setOpcode(MI, Mips_BEQZALC);
549
550 if (HasRs)
551 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
552
553 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
554 MCOperand_CreateImm0(MI, Imm);
555
556 return MCDisassembler_Success;
557 }
558
DecodeDaddiGroupBranch_4(MCInst * MI,uint32_t insn,uint64_t Address,MCRegisterInfo * Decoder)559 static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn,
560 uint64_t Address, MCRegisterInfo *Decoder)
561 {
562 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
563 // (otherwise we would have matched the ADDI instruction from the earlier
564 // ISA's instead).
565 //
566 // We have:
567 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
568 // BNVC if rs >= rt
569 // BNEZALC if rs == 0 && rt != 0
570 // BNEC if rs < rt && rs != 0
571
572 uint32_t Rs = fieldFromInstruction(insn, 21, 5);
573 uint32_t Rt = fieldFromInstruction(insn, 16, 5);
574 uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
575 bool HasRs = false;
576
577 if (Rs >= Rt) {
578 MCInst_setOpcode(MI, Mips_BNVC);
579 HasRs = true;
580 } else if (Rs != 0 && Rs < Rt) {
581 MCInst_setOpcode(MI, Mips_BNEC);
582 HasRs = true;
583 } else
584 MCInst_setOpcode(MI, Mips_BNEZALC);
585
586 if (HasRs)
587 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
588
589 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
590 MCOperand_CreateImm0(MI, Imm);
591
592 return MCDisassembler_Success;
593 }
594
DecodeBlezlGroupBranch_4(MCInst * MI,uint32_t insn,uint64_t Address,MCRegisterInfo * Decoder)595 static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn,
596 uint64_t Address, MCRegisterInfo *Decoder)
597 {
598 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
599 // (otherwise we would have matched the BLEZL instruction from the earlier
600 // ISA's instead).
601 //
602 // We have:
603 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
604 // Invalid if rs == 0
605 // BLEZC if rs == 0 && rt != 0
606 // BGEZC if rs == rt && rt != 0
607 // BGEC if rs != rt && rs != 0 && rt != 0
608
609 uint32_t Rs = fieldFromInstruction(insn, 21, 5);
610 uint32_t Rt = fieldFromInstruction(insn, 16, 5);
611 uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
612 bool HasRs = false;
613
614 if (Rt == 0)
615 return MCDisassembler_Fail;
616 else if (Rs == 0)
617 MCInst_setOpcode(MI, Mips_BLEZC);
618 else if (Rs == Rt)
619 MCInst_setOpcode(MI, Mips_BGEZC);
620 else {
621 HasRs = true;
622 MCInst_setOpcode(MI, Mips_BGEC);
623 }
624
625 if (HasRs)
626 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
627
628 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
629
630 MCOperand_CreateImm0(MI, Imm);
631
632 return MCDisassembler_Success;
633 }
634
DecodeBgtzlGroupBranch_4(MCInst * MI,uint32_t insn,uint64_t Address,MCRegisterInfo * Decoder)635 static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn,
636 uint64_t Address, MCRegisterInfo *Decoder)
637 {
638 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
639 // (otherwise we would have matched the BGTZL instruction from the earlier
640 // ISA's instead).
641 //
642 // We have:
643 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
644 // Invalid if rs == 0
645 // BGTZC if rs == 0 && rt != 0
646 // BLTZC if rs == rt && rt != 0
647 // BLTC if rs != rt && rs != 0 && rt != 0
648
649 bool HasRs = false;
650
651 uint32_t Rs = fieldFromInstruction(insn, 21, 5);
652 uint32_t Rt = fieldFromInstruction(insn, 16, 5);
653 uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
654
655 if (Rt == 0)
656 return MCDisassembler_Fail;
657 else if (Rs == 0)
658 MCInst_setOpcode(MI, Mips_BGTZC);
659 else if (Rs == Rt)
660 MCInst_setOpcode(MI, Mips_BLTZC);
661 else {
662 MCInst_setOpcode(MI, Mips_BLTC);
663 HasRs = true;
664 }
665
666 if (HasRs)
667 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
668
669 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
670 MCOperand_CreateImm0(MI, Imm);
671
672 return MCDisassembler_Success;
673 }
674
DecodeBgtzGroupBranch_4(MCInst * MI,uint32_t insn,uint64_t Address,MCRegisterInfo * Decoder)675 static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn,
676 uint64_t Address, MCRegisterInfo *Decoder)
677 {
678 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
679 // (otherwise we would have matched the BGTZ instruction from the earlier
680 // ISA's instead).
681 //
682 // We have:
683 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
684 // BGTZ if rt == 0
685 // BGTZALC if rs == 0 && rt != 0
686 // BLTZALC if rs != 0 && rs == rt
687 // BLTUC if rs != 0 && rs != rt
688
689 uint32_t Rs = fieldFromInstruction(insn, 21, 5);
690 uint32_t Rt = fieldFromInstruction(insn, 16, 5);
691 uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
692 bool HasRs = false;
693 bool HasRt = false;
694
695 if (Rt == 0) {
696 MCInst_setOpcode(MI, Mips_BGTZ);
697 HasRs = true;
698 } else if (Rs == 0) {
699 MCInst_setOpcode(MI, Mips_BGTZALC);
700 HasRt = true;
701 } else if (Rs == Rt) {
702 MCInst_setOpcode(MI, Mips_BLTZALC);
703 HasRs = true;
704 } else {
705 MCInst_setOpcode(MI, Mips_BLTUC);
706 HasRs = true;
707 HasRt = true;
708 }
709
710 if (HasRs)
711 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
712
713 if (HasRt)
714 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
715
716 MCOperand_CreateImm0(MI, Imm);
717
718 return MCDisassembler_Success;
719 }
720
DecodeBlezGroupBranch_4(MCInst * MI,uint32_t insn,uint64_t Address,MCRegisterInfo * Decoder)721 static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn,
722 uint64_t Address, MCRegisterInfo *Decoder)
723 {
724 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
725 // (otherwise we would have matched the BLEZL instruction from the earlier
726 // ISA's instead).
727 //
728 // We have:
729 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
730 // Invalid if rs == 0
731 // BLEZALC if rs == 0 && rt != 0
732 // BGEZALC if rs == rt && rt != 0
733 // BGEUC if rs != rt && rs != 0 && rt != 0
734
735 uint32_t Rs = fieldFromInstruction(insn, 21, 5);
736 uint32_t Rt = fieldFromInstruction(insn, 16, 5);
737 uint32_t Imm = (uint32_t)SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
738 bool HasRs = false;
739
740 if (Rt == 0)
741 return MCDisassembler_Fail;
742 else if (Rs == 0)
743 MCInst_setOpcode(MI, Mips_BLEZALC);
744 else if (Rs == Rt)
745 MCInst_setOpcode(MI, Mips_BGEZALC);
746 else {
747 HasRs = true;
748 MCInst_setOpcode(MI, Mips_BGEUC);
749 }
750
751 if (HasRs)
752 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
753
754 MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
755
756 MCOperand_CreateImm0(MI, Imm);
757
758 return MCDisassembler_Success;
759 }
760
DecodeCPU16RegsRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)761 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
762 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
763 {
764 return MCDisassembler_Fail;
765 }
766
DecodeGPR64RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)767 static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
768 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
769 {
770 unsigned Reg;
771
772 if (RegNo > 31)
773 return MCDisassembler_Fail;
774
775 Reg = getReg(Decoder, Mips_GPR64RegClassID, RegNo);
776 MCOperand_CreateReg0(Inst, Reg);
777 return MCDisassembler_Success;
778 }
779
DecodeGPR32RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)780 static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
781 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
782 {
783 unsigned Reg;
784
785 if (RegNo > 31)
786 return MCDisassembler_Fail;
787
788 Reg = getReg(Decoder, Mips_GPR32RegClassID, RegNo);
789 MCOperand_CreateReg0(Inst, Reg);
790 return MCDisassembler_Success;
791 }
792
DecodePtrRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)793 static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
794 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
795 {
796 if (Inst->csh->mode & CS_MODE_64)
797 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
798
799 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
800 }
801
DecodeDSPRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)802 static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst,
803 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
804 {
805 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
806 }
807
DecodeFGR64RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)808 static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
809 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
810 {
811 unsigned Reg;
812
813 if (RegNo > 31)
814 return MCDisassembler_Fail;
815
816 Reg = getReg(Decoder, Mips_FGR64RegClassID, RegNo);
817 MCOperand_CreateReg0(Inst, Reg);
818 return MCDisassembler_Success;
819 }
820
DecodeFGR32RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)821 static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
822 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
823 {
824 unsigned Reg;
825
826 if (RegNo > 31)
827 return MCDisassembler_Fail;
828
829 Reg = getReg(Decoder, Mips_FGR32RegClassID, RegNo);
830 MCOperand_CreateReg0(Inst, Reg);
831 return MCDisassembler_Success;
832 }
833
DecodeCCRRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)834 static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
835 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
836 {
837 unsigned Reg;
838
839 if (RegNo > 31)
840 return MCDisassembler_Fail;
841
842 Reg = getReg(Decoder, Mips_CCRRegClassID, RegNo);
843 MCOperand_CreateReg0(Inst, Reg);
844 return MCDisassembler_Success;
845 }
846
DecodeFCCRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)847 static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
848 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
849 {
850 unsigned Reg;
851
852 if (RegNo > 7)
853 return MCDisassembler_Fail;
854
855 Reg = getReg(Decoder, Mips_FCCRegClassID, RegNo);
856 MCOperand_CreateReg0(Inst, Reg);
857 return MCDisassembler_Success;
858 }
859
DecodeCCRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)860 static DecodeStatus DecodeCCRegisterClass(MCInst *Inst,
861 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
862 {
863 unsigned Reg;
864
865 if (RegNo > 7)
866 return MCDisassembler_Fail;
867
868 Reg = getReg(Decoder, Mips_CCRegClassID, RegNo);
869 MCOperand_CreateReg0(Inst, Reg);
870 return MCDisassembler_Success;
871 }
872
DecodeFGRCCRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)873 static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst,
874 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
875 {
876 unsigned Reg;
877
878 if (RegNo > 31)
879 return MCDisassembler_Fail;
880
881 Reg = getReg(Decoder, Mips_FGRCCRegClassID, RegNo);
882 MCOperand_CreateReg0(Inst, Reg);
883 return MCDisassembler_Success;
884 }
885
DecodeMem(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)886 static DecodeStatus DecodeMem(MCInst *Inst,
887 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
888 {
889 int Offset = SignExtend32(Insn & 0xffff, 16);
890 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
891 unsigned Base = fieldFromInstruction(Insn, 21, 5);
892
893 Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
894 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
895
896 if (MCInst_getOpcode(Inst) == Mips_SC){
897 MCOperand_CreateReg0(Inst, Reg);
898 }
899
900 MCOperand_CreateReg0(Inst, Reg);
901 MCOperand_CreateReg0(Inst, Base);
902 MCOperand_CreateImm0(Inst, Offset);
903
904 return MCDisassembler_Success;
905 }
906
DecodeCachePref(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)907 static DecodeStatus DecodeCachePref(MCInst *Inst,
908 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
909 {
910 int Offset = SignExtend32(Insn & 0xffff, 16);
911 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
912 unsigned Base = fieldFromInstruction(Insn, 21, 5);
913
914 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
915
916 MCOperand_CreateReg0(Inst, Base);
917 MCOperand_CreateImm0(Inst, Offset);
918 MCOperand_CreateImm0(Inst, Hint);
919
920 return MCDisassembler_Success;
921 }
922
DecodeMSA128Mem(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)923 static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn,
924 uint64_t Address, MCRegisterInfo *Decoder)
925 {
926 int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10);
927 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
928 unsigned Base = fieldFromInstruction(Insn, 11, 5);
929
930 Reg = getReg(Decoder, Mips_MSA128BRegClassID, Reg);
931 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
932
933 MCOperand_CreateReg0(Inst, Reg);
934 MCOperand_CreateReg0(Inst, Base);
935 // MCOperand_CreateImm0(Inst, Offset);
936
937 // The immediate field of an LD/ST instruction is scaled which means it must
938 // be multiplied (when decoding) by the size (in bytes) of the instructions'
939 // data format.
940 // .b - 1 byte
941 // .h - 2 bytes
942 // .w - 4 bytes
943 // .d - 8 bytes
944 switch(MCInst_getOpcode(Inst)) {
945 default:
946 //assert (0 && "Unexpected instruction");
947 return MCDisassembler_Fail;
948 break;
949 case Mips_LD_B:
950 case Mips_ST_B:
951 MCOperand_CreateImm0(Inst, Offset);
952 break;
953 case Mips_LD_H:
954 case Mips_ST_H:
955 MCOperand_CreateImm0(Inst, Offset * 2);
956 break;
957 case Mips_LD_W:
958 case Mips_ST_W:
959 MCOperand_CreateImm0(Inst, Offset * 4);
960 break;
961 case Mips_LD_D:
962 case Mips_ST_D:
963 MCOperand_CreateImm0(Inst, Offset * 8);
964 break;
965 }
966
967 return MCDisassembler_Success;
968 }
969
DecodeMemMMImm12(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)970 static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
971 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
972 {
973 int Offset = SignExtend32(Insn & 0x0fff, 12);
974 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
975 unsigned Base = fieldFromInstruction(Insn, 16, 5);
976
977 Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
978 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
979
980 if (MCInst_getOpcode(Inst) == Mips_SC_MM)
981 MCOperand_CreateReg0(Inst, Reg);
982
983 MCOperand_CreateReg0(Inst, Reg);
984 MCOperand_CreateReg0(Inst, Base);
985 MCOperand_CreateImm0(Inst, Offset);
986
987 return MCDisassembler_Success;
988 }
989
DecodeMemMMImm16(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)990 static DecodeStatus DecodeMemMMImm16(MCInst *Inst,
991 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
992 {
993 int Offset = SignExtend32(Insn & 0xffff, 16);
994 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
995 unsigned Base = fieldFromInstruction(Insn, 16, 5);
996
997 Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
998 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
999
1000 MCOperand_CreateReg0(Inst, Reg);
1001 MCOperand_CreateReg0(Inst, Base);
1002 MCOperand_CreateImm0(Inst, Offset);
1003
1004 return MCDisassembler_Success;
1005 }
1006
DecodeFMem(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1007 static DecodeStatus DecodeFMem(MCInst *Inst,
1008 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1009 {
1010 int Offset = SignExtend32(Insn & 0xffff, 16);
1011 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1012 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1013
1014 Reg = getReg(Decoder, Mips_FGR64RegClassID, Reg);
1015 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1016
1017 MCOperand_CreateReg0(Inst, Reg);
1018 MCOperand_CreateReg0(Inst, Base);
1019 MCOperand_CreateImm0(Inst, Offset);
1020
1021 return MCDisassembler_Success;
1022 }
1023
DecodeCOP2Mem(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1024 static DecodeStatus DecodeCOP2Mem(MCInst *Inst,
1025 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1026 {
1027 int Offset = SignExtend32(Insn & 0xffff, 16);
1028 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1029 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1030
1031 Reg = getReg(Decoder, Mips_COP2RegClassID, Reg);
1032 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1033
1034 MCOperand_CreateReg0(Inst, Reg);
1035 MCOperand_CreateReg0(Inst, Base);
1036 MCOperand_CreateImm0(Inst, Offset);
1037
1038 return MCDisassembler_Success;
1039 }
1040
DecodeCOP3Mem(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1041 static DecodeStatus DecodeCOP3Mem(MCInst *Inst,
1042 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1043 {
1044 int Offset = SignExtend32(Insn & 0xffff, 16);
1045 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1046 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1047
1048 Reg = getReg(Decoder, Mips_COP3RegClassID, Reg);
1049 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1050
1051 MCOperand_CreateReg0(Inst, Reg);
1052 MCOperand_CreateReg0(Inst, Base);
1053 MCOperand_CreateImm0(Inst, Offset);
1054
1055 return MCDisassembler_Success;
1056 }
1057
DecodeSpecial3LlSc(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1058 static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
1059 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1060 {
1061 int64_t Offset = SignExtend64((Insn >> 7) & 0x1ff, 9);
1062 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1063 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1064
1065 Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt);
1066 Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
1067
1068 if (MCInst_getOpcode(Inst) == Mips_SC_R6 ||
1069 MCInst_getOpcode(Inst) == Mips_SCD_R6) {
1070 MCOperand_CreateReg0(Inst, Rt);
1071 }
1072
1073 MCOperand_CreateReg0(Inst, Rt);
1074 MCOperand_CreateReg0(Inst, Base);
1075 MCOperand_CreateImm0(Inst, Offset);
1076
1077 return MCDisassembler_Success;
1078 }
1079
DecodeHWRegsRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)1080 static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst,
1081 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
1082 {
1083 // Currently only hardware register 29 is supported.
1084 if (RegNo != 29)
1085 return MCDisassembler_Fail;
1086
1087 MCOperand_CreateReg0(Inst, Mips_HWR29);
1088
1089 return MCDisassembler_Success;
1090 }
1091
DecodeAFGR64RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)1092 static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
1093 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
1094 {
1095 unsigned Reg;
1096
1097 if (RegNo > 30 || RegNo % 2)
1098 return MCDisassembler_Fail;
1099
1100 Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2);
1101 MCOperand_CreateReg0(Inst, Reg);
1102
1103 return MCDisassembler_Success;
1104 }
1105
DecodeACC64DSPRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)1106 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst,
1107 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
1108 {
1109 unsigned Reg;
1110
1111 if (RegNo >= 4)
1112 return MCDisassembler_Fail;
1113
1114 Reg = getReg(Decoder, Mips_ACC64DSPRegClassID, RegNo);
1115 MCOperand_CreateReg0(Inst, Reg);
1116 return MCDisassembler_Success;
1117 }
1118
DecodeHI32DSPRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)1119 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
1120 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
1121 {
1122 unsigned Reg;
1123
1124 if (RegNo >= 4)
1125 return MCDisassembler_Fail;
1126
1127 Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo);
1128 MCOperand_CreateReg0(Inst, Reg);
1129
1130 return MCDisassembler_Success;
1131 }
1132
DecodeLO32DSPRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)1133 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
1134 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
1135 {
1136 unsigned Reg;
1137
1138 if (RegNo >= 4)
1139 return MCDisassembler_Fail;
1140
1141 Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo);
1142 MCOperand_CreateReg0(Inst, Reg);
1143
1144 return MCDisassembler_Success;
1145 }
1146
DecodeMSA128BRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)1147 static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst,
1148 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
1149 {
1150 unsigned Reg;
1151
1152 if (RegNo > 31)
1153 return MCDisassembler_Fail;
1154
1155 Reg = getReg(Decoder, Mips_MSA128BRegClassID, RegNo);
1156 MCOperand_CreateReg0(Inst, Reg);
1157
1158 return MCDisassembler_Success;
1159 }
1160
DecodeMSA128HRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)1161 static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst,
1162 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
1163 {
1164 unsigned Reg;
1165
1166 if (RegNo > 31)
1167 return MCDisassembler_Fail;
1168
1169 Reg = getReg(Decoder, Mips_MSA128HRegClassID, RegNo);
1170 MCOperand_CreateReg0(Inst, Reg);
1171
1172 return MCDisassembler_Success;
1173 }
1174
DecodeMSA128WRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)1175 static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
1176 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
1177 {
1178 unsigned Reg;
1179
1180 if (RegNo > 31)
1181 return MCDisassembler_Fail;
1182
1183 Reg = getReg(Decoder, Mips_MSA128WRegClassID, RegNo);
1184 MCOperand_CreateReg0(Inst, Reg);
1185
1186 return MCDisassembler_Success;
1187 }
1188
DecodeMSA128DRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)1189 static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
1190 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
1191 {
1192 unsigned Reg;
1193
1194 if (RegNo > 31)
1195 return MCDisassembler_Fail;
1196
1197 Reg = getReg(Decoder, Mips_MSA128DRegClassID, RegNo);
1198 MCOperand_CreateReg0(Inst, Reg);
1199
1200 return MCDisassembler_Success;
1201 }
1202
DecodeMSACtrlRegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)1203 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
1204 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
1205 {
1206 unsigned Reg;
1207
1208 if (RegNo > 7)
1209 return MCDisassembler_Fail;
1210
1211 Reg = getReg(Decoder, Mips_MSACtrlRegClassID, RegNo);
1212 MCOperand_CreateReg0(Inst, Reg);
1213
1214 return MCDisassembler_Success;
1215 }
1216
DecodeCOP2RegisterClass(MCInst * Inst,unsigned RegNo,uint64_t Address,MCRegisterInfo * Decoder)1217 static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
1218 unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
1219 {
1220 unsigned Reg;
1221
1222 if (RegNo > 31)
1223 return MCDisassembler_Fail;
1224
1225 Reg = getReg(Decoder, Mips_COP2RegClassID, RegNo);
1226 MCOperand_CreateReg0(Inst, Reg);
1227
1228 return MCDisassembler_Success;
1229 }
1230
DecodeBranchTarget(MCInst * Inst,unsigned Offset,uint64_t Address,MCRegisterInfo * Decoder)1231 static DecodeStatus DecodeBranchTarget(MCInst *Inst,
1232 unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
1233 {
1234 uint64_t TargetAddress = (SignExtend32(Offset, 16) * 4) + Address + 4;
1235 MCOperand_CreateImm0(Inst, TargetAddress);
1236
1237 return MCDisassembler_Success;
1238 }
1239
DecodeJumpTarget(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1240 static DecodeStatus DecodeJumpTarget(MCInst *Inst,
1241 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1242 {
1243 uint64_t TargetAddress = (fieldFromInstruction(Insn, 0, 26) << 2) | ((Address + 4) & ~0x0FFFFFFF);
1244 MCOperand_CreateImm0(Inst, TargetAddress);
1245
1246 return MCDisassembler_Success;
1247 }
1248
DecodeBranchTarget21(MCInst * Inst,unsigned Offset,uint64_t Address,MCRegisterInfo * Decoder)1249 static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
1250 unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
1251 {
1252 int32_t BranchOffset = SignExtend32(Offset, 21) * 4;
1253
1254 MCOperand_CreateImm0(Inst, BranchOffset);
1255
1256 return MCDisassembler_Success;
1257 }
1258
DecodeBranchTarget26(MCInst * Inst,unsigned Offset,uint64_t Address,MCRegisterInfo * Decoder)1259 static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
1260 unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
1261 {
1262 int32_t BranchOffset = SignExtend32(Offset, 26) * 4;
1263
1264 MCOperand_CreateImm0(Inst, BranchOffset);
1265 return MCDisassembler_Success;
1266 }
1267
DecodeBranchTargetMM(MCInst * Inst,unsigned Offset,uint64_t Address,MCRegisterInfo * Decoder)1268 static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
1269 unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
1270 {
1271 int32_t BranchOffset = SignExtend32(Offset, 16) * 2;
1272 MCOperand_CreateImm0(Inst, BranchOffset);
1273
1274 return MCDisassembler_Success;
1275 }
1276
DecodeJumpTargetMM(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1277 static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
1278 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1279 {
1280 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1281 MCOperand_CreateImm0(Inst, JumpOffset);
1282
1283 return MCDisassembler_Success;
1284 }
1285
DecodeSimm16(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1286 static DecodeStatus DecodeSimm16(MCInst *Inst,
1287 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1288 {
1289 MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16));
1290 return MCDisassembler_Success;
1291 }
1292
DecodeLSAImm(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1293 static DecodeStatus DecodeLSAImm(MCInst *Inst,
1294 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1295 {
1296 // We add one to the immediate field as it was encoded as 'imm - 1'.
1297 MCOperand_CreateImm0(Inst, Insn + 1);
1298 return MCDisassembler_Success;
1299 }
1300
DecodeInsSize(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1301 static DecodeStatus DecodeInsSize(MCInst *Inst,
1302 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1303 {
1304 // First we need to grab the pos(lsb) from MCInst.
1305 int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2));
1306 int Size = (int) Insn - Pos + 1;
1307 MCOperand_CreateImm0(Inst, SignExtend32(Size, 16));
1308 return MCDisassembler_Success;
1309 }
1310
DecodeExtSize(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1311 static DecodeStatus DecodeExtSize(MCInst *Inst,
1312 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1313 {
1314 int Size = (int) Insn + 1;
1315 MCOperand_CreateImm0(Inst, SignExtend32(Size, 16));
1316 return MCDisassembler_Success;
1317 }
1318
DecodeSimm19Lsl2(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1319 static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
1320 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1321 {
1322 MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4);
1323 return MCDisassembler_Success;
1324 }
1325
DecodeSimm18Lsl3(MCInst * Inst,unsigned Insn,uint64_t Address,MCRegisterInfo * Decoder)1326 static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
1327 unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
1328 {
1329 MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8);
1330 return MCDisassembler_Success;
1331 }
1332
1333 #endif
1334