1 /* 2 * Copyright 2005 Stephane Marchesin. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef __NOUVEAU_DRM_H__ 26 #define __NOUVEAU_DRM_H__ 27 28 #define NOUVEAU_DRM_HEADER_PATCHLEVEL 16 29 30 #include "drm.h" 31 32 #if defined(__cplusplus) 33 extern "C" { 34 #endif 35 36 /* reserved object handles when using deprecated object APIs - these 37 * are here so that libdrm can allow interoperability with the new 38 * object APIs 39 */ 40 #define NOUVEAU_ABI16_CLIENT 0xffffffff 41 #define NOUVEAU_ABI16_DEVICE 0xdddddddd 42 #define NOUVEAU_ABI16_CHAN(n) (0xcccc0000 | (n)) 43 44 struct drm_nouveau_channel_alloc { 45 uint32_t fb_ctxdma_handle; 46 uint32_t tt_ctxdma_handle; 47 48 int channel; 49 uint32_t pushbuf_domains; 50 51 /* Notifier memory */ 52 uint32_t notifier_handle; 53 54 /* DRM-enforced subchannel assignments */ 55 struct { 56 uint32_t handle; 57 uint32_t grclass; 58 } subchan[8]; 59 uint32_t nr_subchan; 60 }; 61 62 struct drm_nouveau_channel_free { 63 int channel; 64 }; 65 66 struct drm_nouveau_grobj_alloc { 67 int channel; 68 uint32_t handle; 69 int class; 70 }; 71 72 struct drm_nouveau_notifierobj_alloc { 73 uint32_t channel; 74 uint32_t handle; 75 uint32_t size; 76 uint32_t offset; 77 }; 78 79 struct drm_nouveau_gpuobj_free { 80 int channel; 81 uint32_t handle; 82 }; 83 84 /* FIXME : maybe unify {GET,SET}PARAMs */ 85 #define NOUVEAU_GETPARAM_PCI_VENDOR 3 86 #define NOUVEAU_GETPARAM_PCI_DEVICE 4 87 #define NOUVEAU_GETPARAM_BUS_TYPE 5 88 #define NOUVEAU_GETPARAM_FB_PHYSICAL 6 89 #define NOUVEAU_GETPARAM_AGP_PHYSICAL 7 90 #define NOUVEAU_GETPARAM_FB_SIZE 8 91 #define NOUVEAU_GETPARAM_AGP_SIZE 9 92 #define NOUVEAU_GETPARAM_PCI_PHYSICAL 10 93 #define NOUVEAU_GETPARAM_CHIPSET_ID 11 94 #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 95 #define NOUVEAU_GETPARAM_GRAPH_UNITS 13 96 #define NOUVEAU_GETPARAM_PTIMER_TIME 14 97 #define NOUVEAU_GETPARAM_HAS_BO_USAGE 15 98 #define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16 99 struct drm_nouveau_getparam { 100 uint64_t param; 101 uint64_t value; 102 }; 103 104 struct drm_nouveau_setparam { 105 uint64_t param; 106 uint64_t value; 107 }; 108 109 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) 110 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) 111 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) 112 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) 113 #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4) 114 115 #define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */ 116 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 117 #define NOUVEAU_GEM_TILE_16BPP 0x00000001 118 #define NOUVEAU_GEM_TILE_32BPP 0x00000002 119 #define NOUVEAU_GEM_TILE_ZETA 0x00000004 120 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 121 122 struct drm_nouveau_gem_info { 123 __u32 handle; 124 __u32 domain; 125 __u64 size; 126 __u64 offset; 127 __u64 map_handle; 128 __u32 tile_mode; 129 __u32 tile_flags; 130 }; 131 132 struct drm_nouveau_gem_set_tiling { 133 uint32_t handle; 134 uint32_t tile_mode; 135 uint32_t tile_flags; 136 }; 137 138 struct drm_nouveau_gem_new { 139 struct drm_nouveau_gem_info info; 140 __u32 channel_hint; 141 __u32 align; 142 }; 143 144 #define NOUVEAU_GEM_MAX_BUFFERS 1024 145 struct drm_nouveau_gem_pushbuf_bo_presumed { 146 __u32 valid; 147 __u32 domain; 148 __u64 offset; 149 }; 150 151 struct drm_nouveau_gem_pushbuf_bo { 152 __u64 user_priv; 153 __u32 handle; 154 __u32 read_domains; 155 __u32 write_domains; 156 __u32 valid_domains; 157 struct drm_nouveau_gem_pushbuf_bo_presumed presumed; 158 }; 159 160 #define NOUVEAU_GEM_RELOC_LOW (1 << 0) 161 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1) 162 #define NOUVEAU_GEM_RELOC_OR (1 << 2) 163 #define NOUVEAU_GEM_MAX_RELOCS 1024 164 struct drm_nouveau_gem_pushbuf_reloc { 165 __u32 reloc_bo_index; 166 __u32 reloc_bo_offset; 167 __u32 bo_index; 168 __u32 flags; 169 __u32 data; 170 __u32 vor; 171 __u32 tor; 172 }; 173 174 #define NOUVEAU_GEM_MAX_PUSH 512 175 struct drm_nouveau_gem_pushbuf_push { 176 __u32 bo_index; 177 __u32 pad; 178 __u64 offset; 179 __u64 length; 180 }; 181 182 struct drm_nouveau_gem_pushbuf { 183 __u32 channel; 184 __u32 nr_buffers; 185 __u64 buffers; 186 __u32 nr_relocs; 187 __u32 nr_push; 188 __u64 relocs; 189 __u64 push; 190 __u32 suffix0; 191 __u32 suffix1; 192 __u64 vram_available; 193 __u64 gart_available; 194 }; 195 196 #define NOUVEAU_GEM_PUSHBUF_2_FENCE_WAIT 0x00000001 197 #define NOUVEAU_GEM_PUSHBUF_2_FENCE_EMIT 0x00000002 198 struct drm_nouveau_gem_pushbuf_2 { 199 uint32_t channel; 200 uint32_t flags; 201 uint32_t nr_push; 202 uint32_t nr_buffers; 203 int32_t fence; /* in/out, depends on flags */ 204 uint32_t pad; 205 uint64_t push; /* in raw hw format */ 206 uint64_t buffers; /* ptr to drm_nouveau_gem_pushbuf_bo */ 207 uint64_t vram_available; 208 uint64_t gart_available; 209 }; 210 211 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 212 #define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002 213 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 214 struct drm_nouveau_gem_cpu_prep { 215 __u32 handle; 216 __u32 flags; 217 }; 218 219 struct drm_nouveau_gem_cpu_fini { 220 __u32 handle; 221 }; 222 223 #define NOUVEAU_GEM_AS_SPARSE 0x00000001 224 struct drm_nouveau_gem_as_alloc { 225 uint64_t pages; /* in, page length */ 226 uint32_t page_size; /* in, byte page size */ 227 uint32_t flags; /* in, flags of address space */ 228 uint64_t align; /* in, requested alignment in bytes */ 229 uint64_t address; /* in/out, non-zero for fixed address allocation */ 230 }; 231 232 struct drm_nouveau_gem_as_free { 233 uint64_t address; /* in, byte address */ 234 }; 235 236 enum nouveau_bus_type { 237 NV_AGP = 0, 238 NV_PCI = 1, 239 NV_PCIE = 2, 240 }; 241 242 struct drm_nouveau_sarea { 243 }; 244 245 #define NOUVEAU_GEM_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT 8 246 #define NOUVEAU_GEM_CHANNEL_GR_ERROR_SW_NOTIFY 13 247 #define NOUVEAU_GEM_CHANNEL_FIFO_ERROR_MMU_ERR_FLT 31 248 #define NOUVEAU_GEM_CHANNEL_PBDMA_ERROR 32 249 struct drm_nouveau_gem_set_error_notifier { 250 uint32_t channel; 251 uint32_t buffer; 252 uint32_t offset; /* in bytes, u32-aligned */ 253 }; 254 255 struct drm_nouveau_gem_map { 256 uint32_t handle; 257 uint32_t domain; 258 uint64_t offset; 259 uint64_t delta; 260 uint64_t length; 261 uint32_t tile_mode; 262 uint32_t tile_flags; 263 }; 264 265 struct drm_nouveau_gem_unmap { 266 uint32_t handle; 267 uint32_t pad; 268 uint64_t offset; 269 uint64_t delta; 270 uint64_t length; 271 }; 272 273 #define DRM_NOUVEAU_GETPARAM 0x00 274 #define DRM_NOUVEAU_SETPARAM 0x01 275 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 276 #define DRM_NOUVEAU_CHANNEL_FREE 0x03 277 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 278 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 279 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 280 #define DRM_NOUVEAU_NVIF 0x07 281 #define DRM_NOUVEAU_GEM_NEW 0x40 282 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 283 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 284 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43 285 #define DRM_NOUVEAU_GEM_INFO 0x44 286 287 /* The ioctls below are marked as staging */ 288 #define DRM_NOUVEAU_GEM_SET_TILING 0x50 289 #define DRM_NOUVEAU_GEM_PUSHBUF_2 0x51 290 #define DRM_NOUVEAU_GEM_SET_INFO 0x52 291 #define DRM_NOUVEAU_GEM_AS_ALLOC 0x53 292 #define DRM_NOUVEAU_GEM_AS_FREE 0x54 293 #define DRM_NOUVEAU_GEM_SET_ERROR_NOTIFIER 0x55 294 #define DRM_NOUVEAU_GEM_MAP 0x56 295 #define DRM_NOUVEAU_GEM_UNMAP 0x57 296 297 #if defined(__cplusplus) 298 } 299 #endif 300 #endif /* __NOUVEAU_DRM_H__ */ 301