1; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s 2; We have to XFAIL this temporarily because of the reversion of r229675. 3; XFAIL: * 4 5; Currently, the following IR assembly generates a KILL instruction between 6; the bitwise-and instruction and the return instruction. We verify that the 7; delay slot filler ignores such KILL instructions by filling the slot of the 8; return instruction properly. 9define signext i32 @f1(i32 signext %a, i32 signext %b) { 10entry: 11 ; CHECK: jr $ra 12 ; CHECK-NEXT: and $2, $4, $5 13 14 %r = and i32 %a, %b 15 ret i32 %r 16} 17