1; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ 2; RUN: -check-prefixes=ALL,GP32,NOT-R6,NOT-R2-R6 3; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ 4; RUN: -check-prefixes=ALL,GP32,NOT-R6,NOT-R2-R6 5; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ 6; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 7; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ 8; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 9; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ 10; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 11; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ 12; RUN: -check-prefixes=ALL,GP32,R6,R2-R6 13 14; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ 15; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 16; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ 17; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 18; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ 19; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 20; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ 21; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 22; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ 23; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 24; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ 25; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 26; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ 27; RUN: -check-prefixes=ALL,64R6,R6,R2-R6 28 29; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 30; RUN: -check-prefixes=ALL,MMR3,MM32 31; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 32; RUN: -check-prefixes=ALL,MMR6,MM32 33; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \ 34; RUN: -check-prefixes=ALL,MMR6,MM64 35 36define signext i1 @srem_i1(i1 signext %a, i1 signext %b) { 37entry: 38; ALL-LABEL: srem_i1: 39 40 ; NOT-R6: div $zero, $4, $5 41 ; NOT-R6: teq $5, $zero, 7 42 ; NOT-R6: mfhi $[[T0:[0-9]+]] 43 ; NOT-R6: sll $[[T1:[0-9]+]], $[[T0]], 31 44 ; NOT-R6: sra $2, $[[T1]], 31 45 46 ; R6: mod $[[T0:[0-9]+]], $4, $5 47 ; R6: teq $5, $zero, 7 48 ; R6: sll $[[T3:[0-9]+]], $[[T0]], 31 49 ; R6: sra $2, $[[T3]], 31 50 51 ; MMR3: div $zero, $4, $5 52 ; MMR3: teq $5, $zero, 7 53 ; MMR3: mfhi $[[T0:[0-9]+]] 54 ; MMR3: sll $[[T1:[0-9]+]], $[[T0]], 31 55 ; MMR3: sra $2, $[[T1]], 31 56 57 ; MMR6: mod $[[T0:[0-9]+]], $4, $5 58 ; MMR6: teq $5, $zero, 7 59 ; MMR6: sll $[[T1:[0-9]+]], $[[T0]], 31 60 ; MMR6: sra $2, $[[T1]], 31 61 62 %r = srem i1 %a, %b 63 ret i1 %r 64} 65 66define signext i8 @srem_i8(i8 signext %a, i8 signext %b) { 67entry: 68; ALL-LABEL: srem_i8: 69 70 ; NOT-R2-R6: div $zero, $4, $5 71 ; NOT-R2-R6: teq $5, $zero, 7 72 ; NOT-R2-R6: mfhi $[[T0:[0-9]+]] 73 ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24 74 ; NOT-R2-R6: sra $2, $[[T1]], 24 75 76 ; R2-R5: div $zero, $4, $5 77 ; R2-R5: teq $5, $zero, 7 78 ; R2-R5: mfhi $[[T0:[0-9]+]] 79 ; R2-R5: seb $2, $[[T0]] 80 81 ; R6: mod $[[T0:[0-9]+]], $4, $5 82 ; R6: teq $5, $zero, 7 83 ; R6: seb $2, $[[T0]] 84 85 ; MMR3: div $zero, $4, $5 86 ; MMR3: teq $5, $zero, 7 87 ; MMR3: mfhi $[[T0:[0-9]+]] 88 ; MMR3: seb $2, $[[T0]] 89 90 ; MMR6: mod $[[T0:[0-9]+]], $4, $5 91 ; MMR6: teq $5, $zero, 7 92 ; MMR6: seb $2, $[[T0]] 93 94 %r = srem i8 %a, %b 95 ret i8 %r 96} 97 98define signext i16 @srem_i16(i16 signext %a, i16 signext %b) { 99entry: 100; ALL-LABEL: srem_i16: 101 102 ; NOT-R2-R6: div $zero, $4, $5 103 ; NOT-R2-R6: teq $5, $zero, 7 104 ; NOT-R2-R6: mfhi $[[T0:[0-9]+]] 105 ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16 106 ; NOT-R2-R6: sra $2, $[[T1]], 16 107 108 ; R2-R5: div $zero, $4, $5 109 ; R2-R5: teq $5, $zero, 7 110 ; R2-R5: mfhi $[[T0:[0-9]+]] 111 ; R2-R5: seh $2, $[[T0]] 112 113 ; R6: mod $[[T0:[0-9]+]], $4, $5 114 ; R6: teq $5, $zero, 7 115 ; R6: seh $2, $[[T0]] 116 117 ; MMR3: div $zero, $4, $5 118 ; MMR3: teq $5, $zero, 7 119 ; MMR3: mfhi $[[T0:[0-9]+]] 120 ; MMR3: seh $2, $[[T0]] 121 122 ; MMR6: mod $[[T0:[0-9]+]], $4, $5 123 ; MMR6: teq $5, $zero, 7 124 ; MMR6: seh $2, $[[T0]] 125 126 %r = srem i16 %a, %b 127 ret i16 %r 128} 129 130define signext i32 @srem_i32(i32 signext %a, i32 signext %b) { 131entry: 132; ALL-LABEL: srem_i32: 133 134 ; NOT-R6: div $zero, $4, $5 135 ; NOT-R6: teq $5, $zero, 7 136 ; NOT-R6: mfhi $2 137 138 ; R6: mod $2, $4, $5 139 ; R6: teq $5, $zero, 7 140 141 ; MMR3: div $zero, $4, $5 142 ; MMR3: teq $5, $zero, 7 143 ; MMR3: mfhi $2 144 145 ; MMR6: mod $2, $4, $5 146 ; MMR6: teq $5, $zero, 7 147 148 %r = srem i32 %a, %b 149 ret i32 %r 150} 151 152define signext i64 @srem_i64(i64 signext %a, i64 signext %b) { 153entry: 154; ALL-LABEL: srem_i64: 155 156 ; GP32: lw $25, %call16(__moddi3)($gp) 157 158 ; GP64-NOT-R6: ddiv $zero, $4, $5 159 ; GP64-NOT-R6: teq $5, $zero, 7 160 ; GP64-NOT-R6: mfhi $2 161 162 ; 64R6: dmod $2, $4, $5 163 ; 64R6: teq $5, $zero, 7 164 165 ; MM32: lw $25, %call16(__moddi3)($2) 166 167 ; MM64: dmod $2, $4, $5 168 ; MM64: teq $5, $zero, 7 169 170 %r = srem i64 %a, %b 171 ret i64 %r 172} 173 174define signext i128 @srem_i128(i128 signext %a, i128 signext %b) { 175entry: 176; ALL-LABEL: srem_i128: 177 178 ; GP32: lw $25, %call16(__modti3)($gp) 179 180 ; GP64-NOT-R6: ld $25, %call16(__modti3)($gp) 181 ; 64R6: ld $25, %call16(__modti3)($gp) 182 183 ; MM32: lw $25, %call16(__modti3)($2) 184 185 ; MM64: ld $25, %call16(__modti3)($2) 186 187 %r = srem i128 %a, %b 188 ret i128 %r 189} 190