1; Check the miscellaneous logical vector operations added in P8 2; 3; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s 4; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s 5; Test x eqv y 6define <4 x i32> @test_xxleqv(<4 x i32> %x, <4 x i32> %y) nounwind { 7 %tmp = xor <4 x i32> %x, %y 8 %ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1> 9 ret <4 x i32> %ret_val 10; CHECK: xxleqv 34, 34, 35 11} 12 13; Test x xxlnand y 14define <4 x i32> @test_xxlnand(<4 x i32> %x, <4 x i32> %y) nounwind { 15 %tmp = and <4 x i32> %x, %y 16 %ret_val = xor <4 x i32> %tmp, <i32 -1, i32 -1, i32 -1, i32 -1> 17 ret <4 x i32> %ret_val 18; CHECK: xxlnand 34, 34, 35 19} 20 21; Test x xxlorc y 22define <4 x i32> @test_xxlorc(<4 x i32> %x, <4 x i32> %y) nounwind { 23 %tmp = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1> 24 %ret_val = or <4 x i32> %x, %tmp 25 ret <4 x i32> %ret_val 26; CHECK: xxlorc 34, 34, 35 27} 28 29; Test x eqv y 30define <8 x i16> @test_xxleqvv8i16(<8 x i16> %x, <8 x i16> %y) nounwind { 31 %tmp = xor <8 x i16> %x, %y 32 %ret_val = xor <8 x i16> %tmp, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 33 ret <8 x i16> %ret_val 34; CHECK: xxleqv 34, 34, 35 35} 36 37; Test x xxlnand y 38define <8 x i16> @test_xxlnandv8i16(<8 x i16> %x, <8 x i16> %y) nounwind { 39 %tmp = and <8 x i16> %x, %y 40 %ret_val = xor <8 x i16> %tmp, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 41 ret <8 x i16> %ret_val 42; CHECK: xxlnand 34, 34, 35 43} 44 45; Test x xxlorc y 46define <8 x i16> @test_xxlorcv8i16(<8 x i16> %x, <8 x i16> %y) nounwind { 47 %tmp = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 48 %ret_val = or <8 x i16> %x, %tmp 49 ret <8 x i16> %ret_val 50; CHECK: xxlorc 34, 34, 35 51} 52 53