1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef V3D_COMPILER_H
25 #define V3D_COMPILER_H
26
27 #include <assert.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <string.h>
33
34 #include "util/macros.h"
35 #include "common/v3d_debug.h"
36 #include "common/v3d_device_info.h"
37 #include "compiler/nir/nir.h"
38 #include "util/list.h"
39 #include "util/u_math.h"
40
41 #include "qpu/qpu_instr.h"
42 #include "pipe/p_state.h"
43
44 #define V3D_MAX_TEXTURE_SAMPLERS 32
45 #define V3D_MAX_SAMPLES 4
46 #define V3D_MAX_FS_INPUTS 64
47 #define V3D_MAX_VS_INPUTS 64
48
49 struct nir_builder;
50
51 struct v3d_fs_inputs {
52 /**
53 * Array of the meanings of the VPM inputs this shader needs.
54 *
55 * It doesn't include those that aren't part of the VPM, like
56 * point/line coordinates.
57 */
58 struct v3d_varying_slot *input_slots;
59 uint32_t num_inputs;
60 };
61
62 enum qfile {
63 /** An unused source or destination register. */
64 QFILE_NULL,
65
66 /** A physical register, such as the W coordinate payload. */
67 QFILE_REG,
68 /** One of the regsiters for fixed function interactions. */
69 QFILE_MAGIC,
70
71 /**
72 * A virtual register, that will be allocated to actual accumulator
73 * or physical registers later.
74 */
75 QFILE_TEMP,
76 QFILE_UNIF,
77 QFILE_TLB,
78 QFILE_TLBU,
79
80 /**
81 * VPM reads use this with an index value to say what part of the VPM
82 * is being read.
83 */
84 QFILE_VPM,
85
86 /**
87 * Stores an immediate value in the index field that will be used
88 * directly by qpu_load_imm().
89 */
90 QFILE_LOAD_IMM,
91
92 /**
93 * Stores an immediate value in the index field that can be turned
94 * into a small immediate field by qpu_encode_small_immediate().
95 */
96 QFILE_SMALL_IMM,
97 };
98
99 /**
100 * A reference to a QPU register or a virtual temp register.
101 */
102 struct qreg {
103 enum qfile file;
104 uint32_t index;
105 };
106
vir_reg(enum qfile file,uint32_t index)107 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
108 {
109 return (struct qreg){file, index};
110 }
111
112 /**
113 * A reference to an actual register at the QPU level, for register
114 * allocation.
115 */
116 struct qpu_reg {
117 bool magic;
118 int index;
119 };
120
121 struct qinst {
122 /** Entry in qblock->instructions */
123 struct list_head link;
124
125 /**
126 * The instruction being wrapped. Its condition codes, pack flags,
127 * signals, etc. will all be used, with just the register references
128 * being replaced by the contents of qinst->dst and qinst->src[].
129 */
130 struct v3d_qpu_instr qpu;
131
132 /* Pre-register-allocation references to src/dst registers */
133 struct qreg dst;
134 struct qreg src[3];
135 bool cond_is_exec_mask;
136 bool has_implicit_uniform;
137 bool is_last_thrsw;
138
139 /* After vir_to_qpu.c: If instr reads a uniform, which uniform from
140 * the uncompiled stream it is.
141 */
142 int uniform;
143 };
144
145 enum quniform_contents {
146 /**
147 * Indicates that a constant 32-bit value is copied from the program's
148 * uniform contents.
149 */
150 QUNIFORM_CONSTANT,
151 /**
152 * Indicates that the program's uniform contents are used as an index
153 * into the GL uniform storage.
154 */
155 QUNIFORM_UNIFORM,
156
157 /** @{
158 * Scaling factors from clip coordinates to relative to the viewport
159 * center.
160 *
161 * This is used by the coordinate and vertex shaders to produce the
162 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
163 * point offsets from the viewport ccenter.
164 */
165 QUNIFORM_VIEWPORT_X_SCALE,
166 QUNIFORM_VIEWPORT_Y_SCALE,
167 /** @} */
168
169 QUNIFORM_VIEWPORT_Z_OFFSET,
170 QUNIFORM_VIEWPORT_Z_SCALE,
171
172 QUNIFORM_USER_CLIP_PLANE,
173
174 /**
175 * A reference to a V3D 3.x texture config parameter 0 uniform.
176 *
177 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
178 * defines texture type, miplevels, and such. It will be found as a
179 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
180 */
181 QUNIFORM_TEXTURE_CONFIG_P0_0,
182 QUNIFORM_TEXTURE_CONFIG_P0_1,
183 QUNIFORM_TEXTURE_CONFIG_P0_2,
184 QUNIFORM_TEXTURE_CONFIG_P0_3,
185 QUNIFORM_TEXTURE_CONFIG_P0_4,
186 QUNIFORM_TEXTURE_CONFIG_P0_5,
187 QUNIFORM_TEXTURE_CONFIG_P0_6,
188 QUNIFORM_TEXTURE_CONFIG_P0_7,
189 QUNIFORM_TEXTURE_CONFIG_P0_8,
190 QUNIFORM_TEXTURE_CONFIG_P0_9,
191 QUNIFORM_TEXTURE_CONFIG_P0_10,
192 QUNIFORM_TEXTURE_CONFIG_P0_11,
193 QUNIFORM_TEXTURE_CONFIG_P0_12,
194 QUNIFORM_TEXTURE_CONFIG_P0_13,
195 QUNIFORM_TEXTURE_CONFIG_P0_14,
196 QUNIFORM_TEXTURE_CONFIG_P0_15,
197 QUNIFORM_TEXTURE_CONFIG_P0_16,
198 QUNIFORM_TEXTURE_CONFIG_P0_17,
199 QUNIFORM_TEXTURE_CONFIG_P0_18,
200 QUNIFORM_TEXTURE_CONFIG_P0_19,
201 QUNIFORM_TEXTURE_CONFIG_P0_20,
202 QUNIFORM_TEXTURE_CONFIG_P0_21,
203 QUNIFORM_TEXTURE_CONFIG_P0_22,
204 QUNIFORM_TEXTURE_CONFIG_P0_23,
205 QUNIFORM_TEXTURE_CONFIG_P0_24,
206 QUNIFORM_TEXTURE_CONFIG_P0_25,
207 QUNIFORM_TEXTURE_CONFIG_P0_26,
208 QUNIFORM_TEXTURE_CONFIG_P0_27,
209 QUNIFORM_TEXTURE_CONFIG_P0_28,
210 QUNIFORM_TEXTURE_CONFIG_P0_29,
211 QUNIFORM_TEXTURE_CONFIG_P0_30,
212 QUNIFORM_TEXTURE_CONFIG_P0_31,
213 QUNIFORM_TEXTURE_CONFIG_P0_32,
214
215 /**
216 * A reference to a V3D 3.x texture config parameter 1 uniform.
217 *
218 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
219 * has the pointer to the indirect texture state. Our data[] field
220 * will have a packed p1 value, but the address field will be just
221 * which texture unit's texture should be referenced.
222 */
223 QUNIFORM_TEXTURE_CONFIG_P1,
224
225 /* A a V3D 4.x texture config parameter. The high 8 bits will be
226 * which texture or sampler is being sampled, and the driver must
227 * replace the address field with the appropriate address.
228 */
229 QUNIFORM_TMU_CONFIG_P0,
230 QUNIFORM_TMU_CONFIG_P1,
231
232 QUNIFORM_TEXTURE_FIRST_LEVEL,
233
234 QUNIFORM_TEXTURE_WIDTH,
235 QUNIFORM_TEXTURE_HEIGHT,
236 QUNIFORM_TEXTURE_DEPTH,
237 QUNIFORM_TEXTURE_ARRAY_SIZE,
238 QUNIFORM_TEXTURE_LEVELS,
239
240 QUNIFORM_UBO_ADDR,
241
242 QUNIFORM_TEXRECT_SCALE_X,
243 QUNIFORM_TEXRECT_SCALE_Y,
244
245 QUNIFORM_TEXTURE_BORDER_COLOR,
246
247 QUNIFORM_STENCIL,
248
249 QUNIFORM_ALPHA_REF,
250 QUNIFORM_SAMPLE_MASK,
251 };
252
253 struct v3d_varying_slot {
254 uint8_t slot_and_component;
255 };
256
257 static inline struct v3d_varying_slot
v3d_slot_from_slot_and_component(uint8_t slot,uint8_t component)258 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
259 {
260 assert(slot < 255 / 4);
261 return (struct v3d_varying_slot){ (slot << 2) + component };
262 }
263
v3d_slot_get_slot(struct v3d_varying_slot slot)264 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
265 {
266 return slot.slot_and_component >> 2;
267 }
268
v3d_slot_get_component(struct v3d_varying_slot slot)269 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
270 {
271 return slot.slot_and_component & 3;
272 }
273
274 struct v3d_ubo_range {
275 /**
276 * offset in bytes from the start of the ubo where this range is
277 * uploaded.
278 *
279 * Only set once used is set.
280 */
281 uint32_t dst_offset;
282
283 /**
284 * offset in bytes from the start of the gallium uniforms where the
285 * data comes from.
286 */
287 uint32_t src_offset;
288
289 /** size in bytes of this ubo range */
290 uint32_t size;
291 };
292
293 struct v3d_key {
294 void *shader_state;
295 struct {
296 uint8_t swizzle[4];
297 uint8_t return_size;
298 uint8_t return_channels;
299 union {
300 struct {
301 unsigned compare_mode:1;
302 unsigned compare_func:3;
303 bool clamp_s:1;
304 bool clamp_t:1;
305 bool clamp_r:1;
306 };
307 struct {
308 uint16_t msaa_width, msaa_height;
309 };
310 };
311 } tex[V3D_MAX_TEXTURE_SAMPLERS];
312 uint8_t ucp_enables;
313 };
314
315 struct v3d_fs_key {
316 struct v3d_key base;
317 bool depth_enabled;
318 bool is_points;
319 bool is_lines;
320 bool alpha_test;
321 bool point_coord_upper_left;
322 bool light_twoside;
323 bool msaa;
324 bool sample_coverage;
325 bool sample_alpha_to_coverage;
326 bool sample_alpha_to_one;
327 bool clamp_color;
328 bool shade_model_flat;
329 uint8_t nr_cbufs;
330 uint8_t swap_color_rb;
331 /* Mask of which render targets need to be written as 32-bit floats */
332 uint8_t f32_color_rb;
333 uint8_t alpha_test_func;
334 uint8_t logicop_func;
335 uint32_t point_sprite_mask;
336
337 struct pipe_rt_blend_state blend;
338 };
339
340 struct v3d_vs_key {
341 struct v3d_key base;
342
343 struct v3d_varying_slot fs_inputs[V3D_MAX_FS_INPUTS];
344 uint8_t num_fs_inputs;
345
346 bool is_coord;
347 bool per_vertex_point_size;
348 bool clamp_color;
349 };
350
351 /** A basic block of VIR intructions. */
352 struct qblock {
353 struct list_head link;
354
355 struct list_head instructions;
356
357 struct set *predecessors;
358 struct qblock *successors[2];
359
360 int index;
361
362 /* Instruction IPs for the first and last instruction of the block.
363 * Set by qpu_schedule.c.
364 */
365 uint32_t start_qpu_ip;
366 uint32_t end_qpu_ip;
367
368 /* Instruction IP for the branch instruction of the block. Set by
369 * qpu_schedule.c.
370 */
371 uint32_t branch_qpu_ip;
372
373 /** Offset within the uniform stream at the start of the block. */
374 uint32_t start_uniform;
375 /** Offset within the uniform stream of the branch instruction */
376 uint32_t branch_uniform;
377
378 /** @{ used by v3d_vir_live_variables.c */
379 BITSET_WORD *def;
380 BITSET_WORD *use;
381 BITSET_WORD *live_in;
382 BITSET_WORD *live_out;
383 int start_ip, end_ip;
384 /** @} */
385 };
386
387 /**
388 * Compiler state saved across compiler invocations, for any expensive global
389 * setup.
390 */
391 struct v3d_compiler {
392 const struct v3d_device_info *devinfo;
393 struct ra_regs *regs;
394 unsigned int reg_class_phys[3];
395 unsigned int reg_class_phys_or_acc[3];
396 };
397
398 struct v3d_compile {
399 const struct v3d_device_info *devinfo;
400 nir_shader *s;
401 nir_function_impl *impl;
402 struct exec_list *cf_node_list;
403 const struct v3d_compiler *compiler;
404
405 /**
406 * Mapping from nir_register * or nir_ssa_def * to array of struct
407 * qreg for the values.
408 */
409 struct hash_table *def_ht;
410
411 /* For each temp, the instruction generating its value. */
412 struct qinst **defs;
413 uint32_t defs_array_size;
414
415 /**
416 * Inputs to the shader, arranged by TGSI declaration order.
417 *
418 * Not all fragment shader QFILE_VARY reads are present in this array.
419 */
420 struct qreg *inputs;
421 struct qreg *outputs;
422 bool msaa_per_sample_output;
423 struct qreg color_reads[V3D_MAX_SAMPLES];
424 struct qreg sample_colors[V3D_MAX_SAMPLES];
425 uint32_t inputs_array_size;
426 uint32_t outputs_array_size;
427 uint32_t uniforms_array_size;
428
429 /* Booleans for whether the corresponding QFILE_VARY[i] is
430 * flat-shaded. This includes gl_FragColor flat-shading, which is
431 * customized based on the shademodel_flat shader key.
432 */
433 uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
434
435 struct v3d_ubo_range *ubo_ranges;
436 bool *ubo_range_used;
437 uint32_t ubo_ranges_array_size;
438 /** Number of uniform areas tracked in ubo_ranges. */
439 uint32_t num_ubo_ranges;
440 uint32_t next_ubo_dst_offset;
441
442 /* State for whether we're executing on each channel currently. 0 if
443 * yes, otherwise a block number + 1 that the channel jumped to.
444 */
445 struct qreg execute;
446
447 struct qreg line_x, point_x, point_y;
448
449 /**
450 * Instance ID, which comes in before the vertex attribute payload if
451 * the shader record requests it.
452 */
453 struct qreg iid;
454
455 /**
456 * Vertex ID, which comes in before the vertex attribute payload
457 * (after Instance ID) if the shader record requests it.
458 */
459 struct qreg vid;
460
461 /* Fragment shader payload regs. */
462 struct qreg payload_w, payload_w_centroid, payload_z;
463
464 uint8_t vattr_sizes[V3D_MAX_VS_INPUTS];
465 uint32_t num_vpm_writes;
466
467 /**
468 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
469 *
470 * This includes those that aren't part of the VPM varyings, like
471 * point/line coordinates.
472 */
473 struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
474
475 /**
476 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
477 * of the output is. Used to emit from the VS in the order that the
478 * FS needs.
479 */
480 struct v3d_varying_slot *output_slots;
481
482 struct pipe_shader_state *shader_state;
483 struct v3d_key *key;
484 struct v3d_fs_key *fs_key;
485 struct v3d_vs_key *vs_key;
486
487 /* Live ranges of temps. */
488 int *temp_start, *temp_end;
489
490 uint32_t *uniform_data;
491 enum quniform_contents *uniform_contents;
492 uint32_t uniform_array_size;
493 uint32_t num_uniforms;
494 uint32_t num_outputs;
495 uint32_t output_position_index;
496 nir_variable *output_color_var[4];
497 uint32_t output_point_size_index;
498 uint32_t output_sample_mask_index;
499
500 struct qreg undef;
501 uint32_t num_temps;
502
503 struct list_head blocks;
504 int next_block_index;
505 struct qblock *cur_block;
506 struct qblock *loop_cont_block;
507 struct qblock *loop_break_block;
508
509 uint64_t *qpu_insts;
510 uint32_t qpu_inst_count;
511 uint32_t qpu_inst_size;
512
513 /* For the FS, the number of varying inputs not counting the
514 * point/line varyings payload
515 */
516 uint32_t num_inputs;
517
518 /**
519 * Number of inputs from num_inputs remaining to be queued to the read
520 * FIFO in the VS/CS.
521 */
522 uint32_t num_inputs_remaining;
523
524 /* Number of inputs currently in the read FIFO for the VS/CS */
525 uint32_t num_inputs_in_fifo;
526
527 /** Next offset in the VPM to read from in the VS/CS */
528 uint32_t vpm_read_offset;
529
530 uint32_t program_id;
531 uint32_t variant_id;
532
533 /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
534 * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
535 * limiting ourselves to the part of the physical reg space.
536 *
537 * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x. On
538 * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
539 * physical reg space in half.
540 */
541 uint8_t threads;
542 struct qinst *last_thrsw;
543 bool last_thrsw_at_top_level;
544
545 bool failed;
546 };
547
548 struct v3d_uniform_list {
549 enum quniform_contents *contents;
550 uint32_t *data;
551 uint32_t count;
552 };
553
554 struct v3d_prog_data {
555 struct v3d_uniform_list uniforms;
556
557 struct v3d_ubo_range *ubo_ranges;
558 uint32_t num_ubo_ranges;
559 uint32_t ubo_size;
560
561 uint8_t num_inputs;
562 uint8_t threads;
563
564 /* For threads > 1, whether the program should be dispatched in the
565 * after-final-THRSW state.
566 */
567 bool single_seg;
568 };
569
570 struct v3d_vs_prog_data {
571 struct v3d_prog_data base;
572
573 bool uses_iid, uses_vid;
574
575 /* Number of components read from each vertex attribute. */
576 uint8_t vattr_sizes[32];
577
578 /* Total number of components read, for the shader state record. */
579 uint32_t vpm_input_size;
580
581 /* Total number of components written, for the shader state record. */
582 uint32_t vpm_output_size;
583 };
584
585 struct v3d_fs_prog_data {
586 struct v3d_prog_data base;
587
588 struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
589
590 /* Array of flat shade flags.
591 *
592 * Each entry is only 24 bits (high 8 bits 0), to match the hardware
593 * packet layout.
594 */
595 uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
596
597 bool writes_z;
598 bool discard;
599 };
600
601 /* Special nir_load_input intrinsic index for loading the current TLB
602 * destination color.
603 */
604 #define V3D_NIR_TLB_COLOR_READ_INPUT 2000000000
605
606 #define V3D_NIR_MS_MASK_OUTPUT 2000000000
607
608 extern const nir_shader_compiler_options v3d_nir_options;
609
610 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo);
611 void v3d_compiler_free(const struct v3d_compiler *compiler);
612 void v3d_optimize_nir(struct nir_shader *s);
613
614 uint64_t *v3d_compile_vs(const struct v3d_compiler *compiler,
615 struct v3d_vs_key *key,
616 struct v3d_vs_prog_data *prog_data,
617 nir_shader *s,
618 int program_id, int variant_id,
619 uint32_t *final_assembly_size);
620
621 uint64_t *v3d_compile_fs(const struct v3d_compiler *compiler,
622 struct v3d_fs_key *key,
623 struct v3d_fs_prog_data *prog_data,
624 nir_shader *s,
625 int program_id, int variant_id,
626 uint32_t *final_assembly_size);
627
628 void v3d_nir_to_vir(struct v3d_compile *c);
629
630 void vir_compile_destroy(struct v3d_compile *c);
631 const char *vir_get_stage_name(struct v3d_compile *c);
632 struct qblock *vir_new_block(struct v3d_compile *c);
633 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
634 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
635 struct qblock *vir_entry_block(struct v3d_compile *c);
636 struct qblock *vir_exit_block(struct v3d_compile *c);
637 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
638 struct qreg src0, struct qreg src1);
639 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
640 struct qreg src0, struct qreg src1);
641 struct qinst *vir_branch_inst(enum v3d_qpu_branch_cond cond, struct qreg src0);
642 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
643 struct qreg vir_uniform(struct v3d_compile *c,
644 enum quniform_contents contents,
645 uint32_t data);
646 void vir_schedule_instructions(struct v3d_compile *c);
647 struct v3d_qpu_instr v3d_qpu_nop(void);
648
649 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
650 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
651 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
652 void vir_set_pf(struct qinst *inst, enum v3d_qpu_pf pf);
653 void vir_set_unpack(struct qinst *inst, int src,
654 enum v3d_qpu_input_unpack unpack);
655
656 struct qreg vir_get_temp(struct v3d_compile *c);
657 void vir_calculate_live_intervals(struct v3d_compile *c);
658 bool vir_has_implicit_uniform(struct qinst *inst);
659 int vir_get_implicit_uniform_src(struct qinst *inst);
660 int vir_get_non_sideband_nsrc(struct qinst *inst);
661 int vir_get_nsrc(struct qinst *inst);
662 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
663 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
664 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
665 bool vir_is_raw_mov(struct qinst *inst);
666 bool vir_is_tex(struct qinst *inst);
667 bool vir_is_add(struct qinst *inst);
668 bool vir_is_mul(struct qinst *inst);
669 bool vir_is_float_input(struct qinst *inst);
670 bool vir_depends_on_flags(struct qinst *inst);
671 bool vir_writes_r3(const struct v3d_device_info *devinfo, struct qinst *inst);
672 bool vir_writes_r4(const struct v3d_device_info *devinfo, struct qinst *inst);
673 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
674 uint8_t vir_channels_written(struct qinst *inst);
675 struct qreg ntq_get_src(struct v3d_compile *c, nir_src src, int i);
676 void ntq_store_dest(struct v3d_compile *c, nir_dest *dest, int chan,
677 struct qreg result);
678 void vir_emit_thrsw(struct v3d_compile *c);
679
680 void vir_dump(struct v3d_compile *c);
681 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
682
683 void vir_validate(struct v3d_compile *c);
684
685 void vir_optimize(struct v3d_compile *c);
686 bool vir_opt_algebraic(struct v3d_compile *c);
687 bool vir_opt_constant_folding(struct v3d_compile *c);
688 bool vir_opt_copy_propagate(struct v3d_compile *c);
689 bool vir_opt_dead_code(struct v3d_compile *c);
690 bool vir_opt_peephole_sf(struct v3d_compile *c);
691 bool vir_opt_small_immediates(struct v3d_compile *c);
692 bool vir_opt_vpm(struct v3d_compile *c);
693 void v3d_nir_lower_blend(nir_shader *s, struct v3d_compile *c);
694 void v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
695 void v3d_nir_lower_txf_ms(nir_shader *s, struct v3d_compile *c);
696 void vir_lower_uniforms(struct v3d_compile *c);
697
698 void v3d33_vir_vpm_read_setup(struct v3d_compile *c, int num_components);
699 void v3d33_vir_vpm_write_setup(struct v3d_compile *c);
700 void v3d33_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
701 void v3d40_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
702
703 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
704 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
705 void qpu_validate(struct v3d_compile *c);
706 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c);
707 bool vir_init_reg_sets(struct v3d_compiler *compiler);
708
709 void vir_PF(struct v3d_compile *c, struct qreg src, enum v3d_qpu_pf pf);
710
711 static inline bool
quniform_contents_is_texture_p0(enum quniform_contents contents)712 quniform_contents_is_texture_p0(enum quniform_contents contents)
713 {
714 return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
715 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
716 V3D_MAX_TEXTURE_SAMPLERS));
717 }
718
719 static inline struct qreg
vir_uniform_ui(struct v3d_compile * c,uint32_t ui)720 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
721 {
722 return vir_uniform(c, QUNIFORM_CONSTANT, ui);
723 }
724
725 static inline struct qreg
vir_uniform_f(struct v3d_compile * c,float f)726 vir_uniform_f(struct v3d_compile *c, float f)
727 {
728 return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
729 }
730
731 #define VIR_ALU0(name, vir_inst, op) \
732 static inline struct qreg \
733 vir_##name(struct v3d_compile *c) \
734 { \
735 return vir_emit_def(c, vir_inst(op, c->undef, \
736 c->undef, c->undef)); \
737 } \
738 static inline struct qinst * \
739 vir_##name##_dest(struct v3d_compile *c, struct qreg dest) \
740 { \
741 return vir_emit_nondef(c, vir_inst(op, dest, \
742 c->undef, c->undef)); \
743 }
744
745 #define VIR_ALU1(name, vir_inst, op) \
746 static inline struct qreg \
747 vir_##name(struct v3d_compile *c, struct qreg a) \
748 { \
749 return vir_emit_def(c, vir_inst(op, c->undef, \
750 a, c->undef)); \
751 } \
752 static inline struct qinst * \
753 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
754 struct qreg a) \
755 { \
756 return vir_emit_nondef(c, vir_inst(op, dest, a, \
757 c->undef)); \
758 }
759
760 #define VIR_ALU2(name, vir_inst, op) \
761 static inline struct qreg \
762 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
763 { \
764 return vir_emit_def(c, vir_inst(op, c->undef, a, b)); \
765 } \
766 static inline struct qinst * \
767 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
768 struct qreg a, struct qreg b) \
769 { \
770 return vir_emit_nondef(c, vir_inst(op, dest, a, b)); \
771 }
772
773 #define VIR_NODST_0(name, vir_inst, op) \
774 static inline struct qinst * \
775 vir_##name(struct v3d_compile *c) \
776 { \
777 return vir_emit_nondef(c, vir_inst(op, c->undef, \
778 c->undef, c->undef)); \
779 }
780
781 #define VIR_NODST_1(name, vir_inst, op) \
782 static inline struct qinst * \
783 vir_##name(struct v3d_compile *c, struct qreg a) \
784 { \
785 return vir_emit_nondef(c, vir_inst(op, c->undef, \
786 a, c->undef)); \
787 }
788
789 #define VIR_NODST_2(name, vir_inst, op) \
790 static inline struct qinst * \
791 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
792 { \
793 return vir_emit_nondef(c, vir_inst(op, c->undef, \
794 a, b)); \
795 }
796
797 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
798 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
799 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
800 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
801 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
802 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
803 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
804 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
805 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
806 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
807 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
808
809 VIR_A_ALU2(FADD)
VIR_A_ALU2(VFPACK)810 VIR_A_ALU2(VFPACK)
811 VIR_A_ALU2(FSUB)
812 VIR_A_ALU2(FMIN)
813 VIR_A_ALU2(FMAX)
814
815 VIR_A_ALU2(ADD)
816 VIR_A_ALU2(SUB)
817 VIR_A_ALU2(SHL)
818 VIR_A_ALU2(SHR)
819 VIR_A_ALU2(ASR)
820 VIR_A_ALU2(ROR)
821 VIR_A_ALU2(MIN)
822 VIR_A_ALU2(MAX)
823 VIR_A_ALU2(UMIN)
824 VIR_A_ALU2(UMAX)
825 VIR_A_ALU2(AND)
826 VIR_A_ALU2(OR)
827 VIR_A_ALU2(XOR)
828 VIR_A_ALU2(VADD)
829 VIR_A_ALU2(VSUB)
830 VIR_A_ALU2(STVPMV)
831 VIR_A_ALU1(NOT)
832 VIR_A_ALU1(NEG)
833 VIR_A_ALU1(FLAPUSH)
834 VIR_A_ALU1(FLBPUSH)
835 VIR_A_ALU1(FLBPOP)
836 VIR_A_ALU1(SETMSF)
837 VIR_A_ALU1(SETREVF)
838 VIR_A_ALU1(TIDX)
839 VIR_A_ALU1(EIDX)
840 VIR_A_ALU1(LDVPMV_IN)
841 VIR_A_ALU1(LDVPMV_OUT)
842
843 VIR_A_ALU0(FXCD)
844 VIR_A_ALU0(XCD)
845 VIR_A_ALU0(FYCD)
846 VIR_A_ALU0(YCD)
847 VIR_A_ALU0(MSF)
848 VIR_A_ALU0(REVF)
849 VIR_A_NODST_1(VPMSETUP)
850 VIR_A_NODST_0(VPMWT)
851 VIR_A_ALU2(FCMP)
852 VIR_A_ALU2(VFMAX)
853
854 VIR_A_ALU1(FROUND)
855 VIR_A_ALU1(FTOIN)
856 VIR_A_ALU1(FTRUNC)
857 VIR_A_ALU1(FTOIZ)
858 VIR_A_ALU1(FFLOOR)
859 VIR_A_ALU1(FTOUZ)
860 VIR_A_ALU1(FCEIL)
861 VIR_A_ALU1(FTOC)
862
863 VIR_A_ALU1(FDX)
864 VIR_A_ALU1(FDY)
865
866 VIR_A_ALU1(ITOF)
867 VIR_A_ALU1(CLZ)
868 VIR_A_ALU1(UTOF)
869
870 VIR_M_ALU2(UMUL24)
871 VIR_M_ALU2(FMUL)
872 VIR_M_ALU2(SMUL24)
873 VIR_M_NODST_2(MULTOP)
874
875 VIR_M_ALU1(MOV)
876 VIR_M_ALU1(FMOV)
877
878 static inline struct qinst *
879 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
880 struct qreg dest, struct qreg src)
881 {
882 struct qinst *mov = vir_MOV_dest(c, dest, src);
883 vir_set_cond(mov, cond);
884 return mov;
885 }
886
887 static inline struct qreg
vir_SEL(struct v3d_compile * c,enum v3d_qpu_cond cond,struct qreg src0,struct qreg src1)888 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
889 struct qreg src0, struct qreg src1)
890 {
891 struct qreg t = vir_get_temp(c);
892 vir_MOV_dest(c, t, src1);
893 vir_MOV_cond(c, cond, t, src0);
894 return t;
895 }
896
897 static inline struct qinst *
vir_NOP(struct v3d_compile * c)898 vir_NOP(struct v3d_compile *c)
899 {
900 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
901 c->undef, c->undef, c->undef));
902 }
903
904 static inline struct qreg
vir_LDTMU(struct v3d_compile * c)905 vir_LDTMU(struct v3d_compile *c)
906 {
907 if (c->devinfo->ver >= 41) {
908 struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
909 c->undef, c->undef);
910 ldtmu->qpu.sig.ldtmu = true;
911
912 return vir_emit_def(c, ldtmu);
913 } else {
914 vir_NOP(c)->qpu.sig.ldtmu = true;
915 return vir_MOV(c, vir_reg(QFILE_MAGIC, V3D_QPU_WADDR_R4));
916 }
917 }
918
919 /*
920 static inline struct qreg
921 vir_LOAD_IMM(struct v3d_compile *c, uint32_t val)
922 {
923 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM, c->undef,
924 vir_reg(QFILE_LOAD_IMM, val), c->undef));
925 }
926
927 static inline struct qreg
928 vir_LOAD_IMM_U2(struct v3d_compile *c, uint32_t val)
929 {
930 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_U2, c->undef,
931 vir_reg(QFILE_LOAD_IMM, val),
932 c->undef));
933 }
934 static inline struct qreg
935 vir_LOAD_IMM_I2(struct v3d_compile *c, uint32_t val)
936 {
937 return vir_emit_def(c, vir_inst(QOP_LOAD_IMM_I2, c->undef,
938 vir_reg(QFILE_LOAD_IMM, val),
939 c->undef));
940 }
941 */
942
943 static inline struct qinst *
vir_BRANCH(struct v3d_compile * c,enum v3d_qpu_cond cond)944 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_cond cond)
945 {
946 /* The actual uniform_data value will be set at scheduling time */
947 return vir_emit_nondef(c, vir_branch_inst(cond, vir_uniform_ui(c, 0)));
948 }
949
950 #define vir_for_each_block(block, c) \
951 list_for_each_entry(struct qblock, block, &c->blocks, link)
952
953 #define vir_for_each_block_rev(block, c) \
954 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
955
956 /* Loop over the non-NULL members of the successors array. */
957 #define vir_for_each_successor(succ, block) \
958 for (struct qblock *succ = block->successors[0]; \
959 succ != NULL; \
960 succ = (succ == block->successors[1] ? NULL : \
961 block->successors[1]))
962
963 #define vir_for_each_inst(inst, block) \
964 list_for_each_entry(struct qinst, inst, &block->instructions, link)
965
966 #define vir_for_each_inst_rev(inst, block) \
967 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
968
969 #define vir_for_each_inst_safe(inst, block) \
970 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
971
972 #define vir_for_each_inst_inorder(inst, c) \
973 vir_for_each_block(_block, c) \
974 vir_for_each_inst(inst, _block)
975
976 #endif /* V3D_COMPILER_H */
977