1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes how to lower LLVM code to machine code. This has two 11 // main components: 12 // 13 // 1. Which ValueTypes are natively supported by the target. 14 // 2. Which operations are supported for supported ValueTypes. 15 // 3. Cost thresholds for alternative implementations of certain operations. 16 // 17 // In addition it has a few other components, like information about FP 18 // immediates. 19 // 20 //===----------------------------------------------------------------------===// 21 22 #ifndef LLVM_TARGET_TARGETLOWERING_H 23 #define LLVM_TARGET_TARGETLOWERING_H 24 25 #include "llvm/CallingConv.h" 26 #include "llvm/InlineAsm.h" 27 #include "llvm/Attributes.h" 28 #include "llvm/ADT/SmallPtrSet.h" 29 #include "llvm/CodeGen/SelectionDAGNodes.h" 30 #include "llvm/CodeGen/RuntimeLibcalls.h" 31 #include "llvm/Support/DebugLoc.h" 32 #include "llvm/Target/TargetCallingConv.h" 33 #include "llvm/Target/TargetMachine.h" 34 #include <climits> 35 #include <map> 36 #include <vector> 37 38 namespace llvm { 39 class AllocaInst; 40 class APFloat; 41 class CallInst; 42 class CCState; 43 class Function; 44 class FastISel; 45 class FunctionLoweringInfo; 46 class ImmutableCallSite; 47 class MachineBasicBlock; 48 class MachineFunction; 49 class MachineFrameInfo; 50 class MachineInstr; 51 class MachineJumpTableInfo; 52 class MCContext; 53 class MCExpr; 54 class SDNode; 55 class SDValue; 56 class SelectionDAG; 57 template<typename T> class SmallVectorImpl; 58 class TargetData; 59 class TargetMachine; 60 class TargetRegisterClass; 61 class TargetLoweringObjectFile; 62 class Value; 63 64 // FIXME: should this be here? 65 namespace TLSModel { 66 enum Model { 67 GeneralDynamic, 68 LocalDynamic, 69 InitialExec, 70 LocalExec 71 }; 72 } 73 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc); 74 75 76 //===----------------------------------------------------------------------===// 77 /// TargetLowering - This class defines information used to lower LLVM code to 78 /// legal SelectionDAG operators that the target instruction selector can accept 79 /// natively. 80 /// 81 /// This class also defines callbacks that targets must implement to lower 82 /// target-specific constructs to SelectionDAG operators. 83 /// 84 class TargetLowering { 85 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT 86 void operator=(const TargetLowering&); // DO NOT IMPLEMENT 87 public: 88 /// LegalizeAction - This enum indicates whether operations are valid for a 89 /// target, and if not, what action should be used to make them valid. 90 enum LegalizeAction { 91 Legal, // The target natively supports this operation. 92 Promote, // This operation should be executed in a larger type. 93 Expand, // Try to expand this to other ops, otherwise use a libcall. 94 Custom // Use the LowerOperation hook to implement custom lowering. 95 }; 96 97 /// LegalizeAction - This enum indicates whether a types are legal for a 98 /// target, and if not, what action should be used to make them valid. 99 enum LegalizeTypeAction { 100 TypeLegal, // The target natively supports this type. 101 TypePromoteInteger, // Replace this integer with a larger one. 102 TypeExpandInteger, // Split this integer into two of half the size. 103 TypeSoftenFloat, // Convert this float to a same size integer type. 104 TypeExpandFloat, // Split this float into two of half the size. 105 TypeScalarizeVector, // Replace this one-element vector with its element. 106 TypeSplitVector, // Split this vector into two of half the size. 107 TypeWidenVector // This vector should be widened into a larger vector. 108 }; 109 110 enum BooleanContent { // How the target represents true/false values. 111 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 112 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 113 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 114 }; 115 getExtendForContent(BooleanContent Content)116 static ISD::NodeType getExtendForContent(BooleanContent Content) { 117 switch (Content) { 118 default: 119 assert(false && "Unknown BooleanContent!"); 120 case UndefinedBooleanContent: 121 // Extend by adding rubbish bits. 122 return ISD::ANY_EXTEND; 123 case ZeroOrOneBooleanContent: 124 // Extend by adding zero bits. 125 return ISD::ZERO_EXTEND; 126 case ZeroOrNegativeOneBooleanContent: 127 // Extend by copying the sign bit. 128 return ISD::SIGN_EXTEND; 129 } 130 } 131 132 /// NOTE: The constructor takes ownership of TLOF. 133 explicit TargetLowering(const TargetMachine &TM, 134 const TargetLoweringObjectFile *TLOF); 135 virtual ~TargetLowering(); 136 getTargetMachine()137 const TargetMachine &getTargetMachine() const { return TM; } getTargetData()138 const TargetData *getTargetData() const { return TD; } getObjFileLowering()139 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } 140 isBigEndian()141 bool isBigEndian() const { return !IsLittleEndian; } isLittleEndian()142 bool isLittleEndian() const { return IsLittleEndian; } getPointerTy()143 MVT getPointerTy() const { return PointerTy; } 144 virtual MVT getShiftAmountTy(EVT LHSTy) const; 145 146 /// isSelectExpensive - Return true if the select operation is expensive for 147 /// this target. isSelectExpensive()148 bool isSelectExpensive() const { return SelectIsExpensive; } 149 150 /// isIntDivCheap() - Return true if integer divide is usually cheaper than 151 /// a sequence of several shifts, adds, and multiplies for this target. isIntDivCheap()152 bool isIntDivCheap() const { return IntDivIsCheap; } 153 154 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of 155 /// srl/add/sra. isPow2DivCheap()156 bool isPow2DivCheap() const { return Pow2DivIsCheap; } 157 158 /// isJumpExpensive() - Return true if Flow Control is an expensive operation 159 /// that should be avoided. isJumpExpensive()160 bool isJumpExpensive() const { return JumpIsExpensive; } 161 162 /// getSetCCResultType - Return the ValueType of the result of SETCC 163 /// operations. Also used to obtain the target's preferred type for 164 /// the condition operand of SELECT and BRCOND nodes. In the case of 165 /// BRCOND the argument passed is MVT::Other since there are no other 166 /// operands to get a type hint from. 167 virtual EVT getSetCCResultType(EVT VT) const; 168 169 /// getCmpLibcallReturnType - Return the ValueType for comparison 170 /// libcalls. Comparions libcalls include floating point comparion calls, 171 /// and Ordered/Unordered check calls on floating point numbers. 172 virtual 173 MVT::SimpleValueType getCmpLibcallReturnType() const; 174 175 /// getBooleanContents - For targets without i1 registers, this gives the 176 /// nature of the high-bits of boolean values held in types wider than i1. 177 /// "Boolean values" are special true/false values produced by nodes like 178 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 179 /// Not to be confused with general values promoted from i1. 180 /// Some cpus distinguish between vectors of boolean and scalars; the isVec 181 /// parameter selects between the two kinds. For example on X86 a scalar 182 /// boolean should be zero extended from i1, while the elements of a vector 183 /// of booleans should be sign extended from i1. getBooleanContents(bool isVec)184 BooleanContent getBooleanContents(bool isVec) const { 185 return isVec ? BooleanVectorContents : BooleanContents; 186 } 187 188 /// getSchedulingPreference - Return target scheduling preference. getSchedulingPreference()189 Sched::Preference getSchedulingPreference() const { 190 return SchedPreferenceInfo; 191 } 192 193 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to 194 /// different scheduling heuristics for different nodes. This function returns 195 /// the preference (or none) for the given node. getSchedulingPreference(SDNode *)196 virtual Sched::Preference getSchedulingPreference(SDNode *) const { 197 return Sched::None; 198 } 199 200 /// getRegClassFor - Return the register class that should be used for the 201 /// specified value type. getRegClassFor(EVT VT)202 virtual TargetRegisterClass *getRegClassFor(EVT VT) const { 203 assert(VT.isSimple() && "getRegClassFor called on illegal type!"); 204 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy]; 205 assert(RC && "This value type is not natively supported!"); 206 return RC; 207 } 208 209 /// getRepRegClassFor - Return the 'representative' register class for the 210 /// specified value type. The 'representative' register class is the largest 211 /// legal super-reg register class for the register class of the value type. 212 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32; 213 /// while the rep register class is GR64 on x86_64. getRepRegClassFor(EVT VT)214 virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const { 215 assert(VT.isSimple() && "getRepRegClassFor called on illegal type!"); 216 const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy]; 217 return RC; 218 } 219 220 /// getRepRegClassCostFor - Return the cost of the 'representative' register 221 /// class for the specified value type. getRepRegClassCostFor(EVT VT)222 virtual uint8_t getRepRegClassCostFor(EVT VT) const { 223 assert(VT.isSimple() && "getRepRegClassCostFor called on illegal type!"); 224 return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy]; 225 } 226 227 /// isTypeLegal - Return true if the target has native support for the 228 /// specified value type. This means that it has a register that directly 229 /// holds it without promotions or expansions. isTypeLegal(EVT VT)230 bool isTypeLegal(EVT VT) const { 231 assert(!VT.isSimple() || 232 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 233 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0; 234 } 235 236 class ValueTypeActionImpl { 237 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum 238 /// that indicates how instruction selection should deal with the type. 239 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE]; 240 241 public: ValueTypeActionImpl()242 ValueTypeActionImpl() { 243 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); 244 } 245 getTypeAction(MVT VT)246 LegalizeTypeAction getTypeAction(MVT VT) const { 247 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy]; 248 } 249 setTypeAction(EVT VT,LegalizeTypeAction Action)250 void setTypeAction(EVT VT, LegalizeTypeAction Action) { 251 unsigned I = VT.getSimpleVT().SimpleTy; 252 ValueTypeActions[I] = Action; 253 } 254 }; 255 getValueTypeActions()256 const ValueTypeActionImpl &getValueTypeActions() const { 257 return ValueTypeActions; 258 } 259 260 /// getTypeAction - Return how we should legalize values of this type, either 261 /// it is already legal (return 'Legal') or we need to promote it to a larger 262 /// type (return 'Promote'), or we need to expand it into multiple registers 263 /// of smaller integer type (return 'Expand'). 'Custom' is not an option. getTypeAction(LLVMContext & Context,EVT VT)264 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const { 265 return getTypeConversion(Context, VT).first; 266 } getTypeAction(MVT VT)267 LegalizeTypeAction getTypeAction(MVT VT) const { 268 return ValueTypeActions.getTypeAction(VT); 269 } 270 271 /// getTypeToTransformTo - For types supported by the target, this is an 272 /// identity function. For types that must be promoted to larger types, this 273 /// returns the larger type to promote to. For integer types that are larger 274 /// than the largest integer register, this contains one step in the expansion 275 /// to get to the smaller register. For illegal floating point types, this 276 /// returns the integer type to transform to. getTypeToTransformTo(LLVMContext & Context,EVT VT)277 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 278 return getTypeConversion(Context, VT).second; 279 } 280 281 /// getTypeToExpandTo - For types supported by the target, this is an 282 /// identity function. For types that must be expanded (i.e. integer types 283 /// that are larger than the largest integer register or illegal floating 284 /// point types), this returns the largest legal type it will be expanded to. getTypeToExpandTo(LLVMContext & Context,EVT VT)285 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 286 assert(!VT.isVector()); 287 while (true) { 288 switch (getTypeAction(Context, VT)) { 289 case TypeLegal: 290 return VT; 291 case TypeExpandInteger: 292 VT = getTypeToTransformTo(Context, VT); 293 break; 294 default: 295 assert(false && "Type is not legal nor is it to be expanded!"); 296 return VT; 297 } 298 } 299 return VT; 300 } 301 302 /// getVectorTypeBreakdown - Vector types are broken down into some number of 303 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 304 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. 305 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. 306 /// 307 /// This method returns the number of registers needed, and the VT for each 308 /// register. It also returns the VT and quantity of the intermediate values 309 /// before they are promoted/expanded. 310 /// 311 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 312 EVT &IntermediateVT, 313 unsigned &NumIntermediates, 314 EVT &RegisterVT) const; 315 316 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the 317 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If 318 /// this is the case, it returns true and store the intrinsic 319 /// information into the IntrinsicInfo that was passed to the function. 320 struct IntrinsicInfo { 321 unsigned opc; // target opcode 322 EVT memVT; // memory VT 323 const Value* ptrVal; // value representing memory location 324 int offset; // offset off of ptrVal 325 unsigned align; // alignment 326 bool vol; // is volatile? 327 bool readMem; // reads memory? 328 bool writeMem; // writes memory? 329 }; 330 getTgtMemIntrinsic(IntrinsicInfo &,const CallInst &,unsigned)331 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 332 unsigned /*Intrinsic*/) const { 333 return false; 334 } 335 336 /// isFPImmLegal - Returns true if the target can instruction select the 337 /// specified FP immediate natively. If false, the legalizer will materialize 338 /// the FP immediate as a load from a constant pool. isFPImmLegal(const APFloat &,EVT)339 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const { 340 return false; 341 } 342 343 /// isShuffleMaskLegal - Targets can use this to indicate that they only 344 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 345 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 346 /// are assumed to be legal. isShuffleMaskLegal(const SmallVectorImpl<int> &,EVT)347 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 348 EVT /*VT*/) const { 349 return true; 350 } 351 352 /// canOpTrap - Returns true if the operation can trap for the value type. 353 /// VT must be a legal type. By default, we optimistically assume most 354 /// operations don't trap except for divide and remainder. 355 virtual bool canOpTrap(unsigned Op, EVT VT) const; 356 357 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 358 /// used by Targets can use this to indicate if there is a suitable 359 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 360 /// pool entry. isVectorClearMaskLegal(const SmallVectorImpl<int> &,EVT)361 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 362 EVT /*VT*/) const { 363 return false; 364 } 365 366 /// getOperationAction - Return how this operation should be treated: either 367 /// it is legal, needs to be promoted to a larger size, needs to be 368 /// expanded to some other code sequence, or the target has a custom expander 369 /// for it. getOperationAction(unsigned Op,EVT VT)370 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 371 if (VT.isExtended()) return Expand; 372 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 373 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; 374 return (LegalizeAction)OpActions[I][Op]; 375 } 376 377 /// isOperationLegalOrCustom - Return true if the specified operation is 378 /// legal on this target or can be made legal with custom lowering. This 379 /// is used to help guide high-level lowering decisions. isOperationLegalOrCustom(unsigned Op,EVT VT)380 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const { 381 return (VT == MVT::Other || isTypeLegal(VT)) && 382 (getOperationAction(Op, VT) == Legal || 383 getOperationAction(Op, VT) == Custom); 384 } 385 386 /// isOperationLegal - Return true if the specified operation is legal on this 387 /// target. isOperationLegal(unsigned Op,EVT VT)388 bool isOperationLegal(unsigned Op, EVT VT) const { 389 return (VT == MVT::Other || isTypeLegal(VT)) && 390 getOperationAction(Op, VT) == Legal; 391 } 392 393 /// getLoadExtAction - Return how this load with extension should be treated: 394 /// either it is legal, needs to be promoted to a larger size, needs to be 395 /// expanded to some other code sequence, or the target has a custom expander 396 /// for it. getLoadExtAction(unsigned ExtType,EVT VT)397 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const { 398 assert(ExtType < ISD::LAST_LOADEXT_TYPE && 399 VT.getSimpleVT() < MVT::LAST_VALUETYPE && 400 "Table isn't big enough!"); 401 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType]; 402 } 403 404 /// isLoadExtLegal - Return true if the specified load with extension is legal 405 /// on this target. isLoadExtLegal(unsigned ExtType,EVT VT)406 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { 407 return VT.isSimple() && getLoadExtAction(ExtType, VT) == Legal; 408 } 409 410 /// getTruncStoreAction - Return how this store with truncation should be 411 /// treated: either it is legal, needs to be promoted to a larger size, needs 412 /// to be expanded to some other code sequence, or the target has a custom 413 /// expander for it. getTruncStoreAction(EVT ValVT,EVT MemVT)414 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const { 415 assert(ValVT.getSimpleVT() < MVT::LAST_VALUETYPE && 416 MemVT.getSimpleVT() < MVT::LAST_VALUETYPE && 417 "Table isn't big enough!"); 418 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy] 419 [MemVT.getSimpleVT().SimpleTy]; 420 } 421 422 /// isTruncStoreLegal - Return true if the specified store with truncation is 423 /// legal on this target. isTruncStoreLegal(EVT ValVT,EVT MemVT)424 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 425 return isTypeLegal(ValVT) && MemVT.isSimple() && 426 getTruncStoreAction(ValVT, MemVT) == Legal; 427 } 428 429 /// getIndexedLoadAction - Return how the indexed load should be treated: 430 /// either it is legal, needs to be promoted to a larger size, needs to be 431 /// expanded to some other code sequence, or the target has a custom expander 432 /// for it. 433 LegalizeAction getIndexedLoadAction(unsigned IdxMode,EVT VT)434 getIndexedLoadAction(unsigned IdxMode, EVT VT) const { 435 assert(IdxMode < ISD::LAST_INDEXED_MODE && 436 VT.getSimpleVT() < MVT::LAST_VALUETYPE && 437 "Table isn't big enough!"); 438 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 439 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4); 440 } 441 442 /// isIndexedLoadLegal - Return true if the specified indexed load is legal 443 /// on this target. isIndexedLoadLegal(unsigned IdxMode,EVT VT)444 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 445 return VT.isSimple() && 446 (getIndexedLoadAction(IdxMode, VT) == Legal || 447 getIndexedLoadAction(IdxMode, VT) == Custom); 448 } 449 450 /// getIndexedStoreAction - Return how the indexed store should be treated: 451 /// either it is legal, needs to be promoted to a larger size, needs to be 452 /// expanded to some other code sequence, or the target has a custom expander 453 /// for it. 454 LegalizeAction getIndexedStoreAction(unsigned IdxMode,EVT VT)455 getIndexedStoreAction(unsigned IdxMode, EVT VT) const { 456 assert(IdxMode < ISD::LAST_INDEXED_MODE && 457 VT.getSimpleVT() < MVT::LAST_VALUETYPE && 458 "Table isn't big enough!"); 459 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy; 460 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f); 461 } 462 463 /// isIndexedStoreLegal - Return true if the specified indexed load is legal 464 /// on this target. isIndexedStoreLegal(unsigned IdxMode,EVT VT)465 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 466 return VT.isSimple() && 467 (getIndexedStoreAction(IdxMode, VT) == Legal || 468 getIndexedStoreAction(IdxMode, VT) == Custom); 469 } 470 471 /// getCondCodeAction - Return how the condition code should be treated: 472 /// either it is legal, needs to be expanded to some other code sequence, 473 /// or the target has a custom expander for it. 474 LegalizeAction getCondCodeAction(ISD::CondCode CC,EVT VT)475 getCondCodeAction(ISD::CondCode CC, EVT VT) const { 476 assert((unsigned)CC < array_lengthof(CondCodeActions) && 477 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 && 478 "Table isn't big enough!"); 479 LegalizeAction Action = (LegalizeAction) 480 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3); 481 assert(Action != Promote && "Can't promote condition code!"); 482 return Action; 483 } 484 485 /// isCondCodeLegal - Return true if the specified condition code is legal 486 /// on this target. isCondCodeLegal(ISD::CondCode CC,EVT VT)487 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const { 488 return getCondCodeAction(CC, VT) == Legal || 489 getCondCodeAction(CC, VT) == Custom; 490 } 491 492 493 /// getTypeToPromoteTo - If the action for this operation is to promote, this 494 /// method returns the ValueType to promote to. getTypeToPromoteTo(unsigned Op,EVT VT)495 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const { 496 assert(getOperationAction(Op, VT) == Promote && 497 "This operation isn't promoted!"); 498 499 // See if this has an explicit type specified. 500 std::map<std::pair<unsigned, MVT::SimpleValueType>, 501 MVT::SimpleValueType>::const_iterator PTTI = 502 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy)); 503 if (PTTI != PromoteToType.end()) return PTTI->second; 504 505 assert((VT.isInteger() || VT.isFloatingPoint()) && 506 "Cannot autopromote this type, add it with AddPromotedToType."); 507 508 EVT NVT = VT; 509 do { 510 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1); 511 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 512 "Didn't find type to promote to!"); 513 } while (!isTypeLegal(NVT) || 514 getOperationAction(Op, NVT) == Promote); 515 return NVT; 516 } 517 518 /// getValueType - Return the EVT corresponding to this LLVM type. 519 /// This is fixed by the LLVM operations except for the pointer size. If 520 /// AllowUnknown is true, this will return MVT::Other for types with no EVT 521 /// counterpart (e.g. structs), otherwise it will assert. 522 EVT getValueType(Type *Ty, bool AllowUnknown = false) const { 523 EVT VT = EVT::getEVT(Ty, AllowUnknown); 524 return VT == MVT::iPTR ? PointerTy : VT; 525 } 526 527 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 528 /// function arguments in the caller parameter area. This is the actual 529 /// alignment, not its logarithm. 530 virtual unsigned getByValTypeAlignment(Type *Ty) const; 531 532 /// getRegisterType - Return the type of registers that this ValueType will 533 /// eventually require. getRegisterType(MVT VT)534 EVT getRegisterType(MVT VT) const { 535 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 536 return RegisterTypeForVT[VT.SimpleTy]; 537 } 538 539 /// getRegisterType - Return the type of registers that this ValueType will 540 /// eventually require. getRegisterType(LLVMContext & Context,EVT VT)541 EVT getRegisterType(LLVMContext &Context, EVT VT) const { 542 if (VT.isSimple()) { 543 assert((unsigned)VT.getSimpleVT().SimpleTy < 544 array_lengthof(RegisterTypeForVT)); 545 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 546 } 547 if (VT.isVector()) { 548 EVT VT1, RegisterVT; 549 unsigned NumIntermediates; 550 (void)getVectorTypeBreakdown(Context, VT, VT1, 551 NumIntermediates, RegisterVT); 552 return RegisterVT; 553 } 554 if (VT.isInteger()) { 555 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 556 } 557 assert(0 && "Unsupported extended type!"); 558 return EVT(MVT::Other); // Not reached 559 } 560 561 /// getNumRegisters - Return the number of registers that this ValueType will 562 /// eventually require. This is one for any types promoted to live in larger 563 /// registers, but may be more than one for types (like i64) that are split 564 /// into pieces. For types like i140, which are first promoted then expanded, 565 /// it is the number of registers needed to hold all the bits of the original 566 /// type. For an i140 on a 32 bit machine this means 5 registers. getNumRegisters(LLVMContext & Context,EVT VT)567 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 568 if (VT.isSimple()) { 569 assert((unsigned)VT.getSimpleVT().SimpleTy < 570 array_lengthof(NumRegistersForVT)); 571 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 572 } 573 if (VT.isVector()) { 574 EVT VT1, VT2; 575 unsigned NumIntermediates; 576 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 577 } 578 if (VT.isInteger()) { 579 unsigned BitWidth = VT.getSizeInBits(); 580 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 581 return (BitWidth + RegWidth - 1) / RegWidth; 582 } 583 assert(0 && "Unsupported extended type!"); 584 return 0; // Not reached 585 } 586 587 /// ShouldShrinkFPConstant - If true, then instruction selection should 588 /// seek to shrink the FP constant of the specified type to a smaller type 589 /// in order to save space and / or reduce runtime. ShouldShrinkFPConstant(EVT)590 virtual bool ShouldShrinkFPConstant(EVT) const { return true; } 591 592 /// hasTargetDAGCombine - If true, the target has custom DAG combine 593 /// transformations that it can perform for the specified node. hasTargetDAGCombine(ISD::NodeType NT)594 bool hasTargetDAGCombine(ISD::NodeType NT) const { 595 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 596 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 597 } 598 599 /// This function returns the maximum number of store operations permitted 600 /// to replace a call to llvm.memset. The value is set by the target at the 601 /// performance threshold for such a replacement. If OptSize is true, 602 /// return the limit for functions that have OptSize attribute. 603 /// @brief Get maximum # of store operations permitted for llvm.memset getMaxStoresPerMemset(bool OptSize)604 unsigned getMaxStoresPerMemset(bool OptSize) const { 605 return OptSize ? maxStoresPerMemsetOptSize : maxStoresPerMemset; 606 } 607 608 /// This function returns the maximum number of store operations permitted 609 /// to replace a call to llvm.memcpy. The value is set by the target at the 610 /// performance threshold for such a replacement. If OptSize is true, 611 /// return the limit for functions that have OptSize attribute. 612 /// @brief Get maximum # of store operations permitted for llvm.memcpy getMaxStoresPerMemcpy(bool OptSize)613 unsigned getMaxStoresPerMemcpy(bool OptSize) const { 614 return OptSize ? maxStoresPerMemcpyOptSize : maxStoresPerMemcpy; 615 } 616 617 /// This function returns the maximum number of store operations permitted 618 /// to replace a call to llvm.memmove. The value is set by the target at the 619 /// performance threshold for such a replacement. If OptSize is true, 620 /// return the limit for functions that have OptSize attribute. 621 /// @brief Get maximum # of store operations permitted for llvm.memmove getMaxStoresPerMemmove(bool OptSize)622 unsigned getMaxStoresPerMemmove(bool OptSize) const { 623 return OptSize ? maxStoresPerMemmoveOptSize : maxStoresPerMemmove; 624 } 625 626 /// This function returns true if the target allows unaligned memory accesses. 627 /// of the specified type. This is used, for example, in situations where an 628 /// array copy/move/set is converted to a sequence of store operations. It's 629 /// use helps to ensure that such replacements don't generate code that causes 630 /// an alignment error (trap) on the target machine. 631 /// @brief Determine if the target supports unaligned memory accesses. allowsUnalignedMemoryAccesses(EVT)632 virtual bool allowsUnalignedMemoryAccesses(EVT) const { 633 return false; 634 } 635 636 /// This function returns true if the target would benefit from code placement 637 /// optimization. 638 /// @brief Determine if the target should perform code placement optimization. shouldOptimizeCodePlacement()639 bool shouldOptimizeCodePlacement() const { 640 return benefitFromCodePlacementOpt; 641 } 642 643 /// getOptimalMemOpType - Returns the target specific optimal type for load 644 /// and store operations as a result of memset, memcpy, and memmove 645 /// lowering. If DstAlign is zero that means it's safe to destination 646 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 647 /// means there isn't a need to check it against alignment requirement, 648 /// probably because the source does not need to be loaded. If 649 /// 'NonScalarIntSafe' is true, that means it's safe to return a 650 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 651 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 652 /// constant so it does not need to be loaded. 653 /// It returns EVT::Other if the type should be determined using generic 654 /// target-independent logic. getOptimalMemOpType(uint64_t,unsigned,unsigned,bool,bool,MachineFunction &)655 virtual EVT getOptimalMemOpType(uint64_t /*Size*/, 656 unsigned /*DstAlign*/, unsigned /*SrcAlign*/, 657 bool /*NonScalarIntSafe*/, 658 bool /*MemcpyStrSrc*/, 659 MachineFunction &/*MF*/) const { 660 return MVT::Other; 661 } 662 663 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp 664 /// to implement llvm.setjmp. usesUnderscoreSetJmp()665 bool usesUnderscoreSetJmp() const { 666 return UseUnderscoreSetJmp; 667 } 668 669 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp 670 /// to implement llvm.longjmp. usesUnderscoreLongJmp()671 bool usesUnderscoreLongJmp() const { 672 return UseUnderscoreLongJmp; 673 } 674 675 /// getStackPointerRegisterToSaveRestore - If a physical register, this 676 /// specifies the register that llvm.savestack/llvm.restorestack should save 677 /// and restore. getStackPointerRegisterToSaveRestore()678 unsigned getStackPointerRegisterToSaveRestore() const { 679 return StackPointerRegisterToSaveRestore; 680 } 681 682 /// getExceptionAddressRegister - If a physical register, this returns 683 /// the register that receives the exception address on entry to a landing 684 /// pad. getExceptionAddressRegister()685 unsigned getExceptionAddressRegister() const { 686 return ExceptionPointerRegister; 687 } 688 689 /// getExceptionSelectorRegister - If a physical register, this returns 690 /// the register that receives the exception typeid on entry to a landing 691 /// pad. getExceptionSelectorRegister()692 unsigned getExceptionSelectorRegister() const { 693 return ExceptionSelectorRegister; 694 } 695 696 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never 697 /// set, the default is 200) getJumpBufSize()698 unsigned getJumpBufSize() const { 699 return JumpBufSize; 700 } 701 702 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes 703 /// (if never set, the default is 0) getJumpBufAlignment()704 unsigned getJumpBufAlignment() const { 705 return JumpBufAlignment; 706 } 707 708 /// getMinStackArgumentAlignment - return the minimum stack alignment of an 709 /// argument. getMinStackArgumentAlignment()710 unsigned getMinStackArgumentAlignment() const { 711 return MinStackArgumentAlignment; 712 } 713 714 /// getMinFunctionAlignment - return the minimum function alignment. 715 /// getMinFunctionAlignment()716 unsigned getMinFunctionAlignment() const { 717 return MinFunctionAlignment; 718 } 719 720 /// getPrefFunctionAlignment - return the preferred function alignment. 721 /// getPrefFunctionAlignment()722 unsigned getPrefFunctionAlignment() const { 723 return PrefFunctionAlignment; 724 } 725 726 /// getPrefLoopAlignment - return the preferred loop alignment. 727 /// getPrefLoopAlignment()728 unsigned getPrefLoopAlignment() const { 729 return PrefLoopAlignment; 730 } 731 732 /// getShouldFoldAtomicFences - return whether the combiner should fold 733 /// fence MEMBARRIER instructions into the atomic intrinsic instructions. 734 /// getShouldFoldAtomicFences()735 bool getShouldFoldAtomicFences() const { 736 return ShouldFoldAtomicFences; 737 } 738 739 /// getInsertFencesFor - return whether the DAG builder should automatically 740 /// insert fences and reduce ordering for atomics. 741 /// getInsertFencesForAtomic()742 bool getInsertFencesForAtomic() const { 743 return InsertFencesForAtomic; 744 } 745 746 /// getPreIndexedAddressParts - returns true by value, base pointer and 747 /// offset pointer and addressing mode by reference if the node's address 748 /// can be legally represented as pre-indexed load / store address. getPreIndexedAddressParts(SDNode *,SDValue &,SDValue &,ISD::MemIndexedMode &,SelectionDAG &)749 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/, 750 SDValue &/*Offset*/, 751 ISD::MemIndexedMode &/*AM*/, 752 SelectionDAG &/*DAG*/) const { 753 return false; 754 } 755 756 /// getPostIndexedAddressParts - returns true by value, base pointer and 757 /// offset pointer and addressing mode by reference if this node can be 758 /// combined with a load / store to form a post-indexed load / store. getPostIndexedAddressParts(SDNode *,SDNode *,SDValue &,SDValue &,ISD::MemIndexedMode &,SelectionDAG &)759 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/, 760 SDValue &/*Base*/, SDValue &/*Offset*/, 761 ISD::MemIndexedMode &/*AM*/, 762 SelectionDAG &/*DAG*/) const { 763 return false; 764 } 765 766 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 767 /// current function. The returned value is a member of the 768 /// MachineJumpTableInfo::JTEntryKind enum. 769 virtual unsigned getJumpTableEncoding() const; 770 771 virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *,const MachineBasicBlock *,unsigned,MCContext &)772 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/, 773 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/, 774 MCContext &/*Ctx*/) const { 775 assert(0 && "Need to implement this hook if target has custom JTIs"); 776 return 0; 777 } 778 779 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 780 /// jumptable. 781 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 782 SelectionDAG &DAG) const; 783 784 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 785 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 786 /// MCExpr. 787 virtual const MCExpr * 788 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 789 unsigned JTI, MCContext &Ctx) const; 790 791 /// isOffsetFoldingLegal - Return true if folding a constant offset 792 /// with the given GlobalAddress is legal. It is frequently not legal in 793 /// PIC relocation models. 794 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 795 796 /// getStackCookieLocation - Return true if the target stores stack 797 /// protector cookies at a fixed offset in some non-standard address 798 /// space, and populates the address space and offset as 799 /// appropriate. getStackCookieLocation(unsigned &,unsigned &)800 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/, 801 unsigned &/*Offset*/) const { 802 return false; 803 } 804 805 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be 806 /// used for loads / stores from the global. getMaximalGlobalOffset()807 virtual unsigned getMaximalGlobalOffset() const { 808 return 0; 809 } 810 811 //===--------------------------------------------------------------------===// 812 // TargetLowering Optimization Methods 813 // 814 815 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two 816 /// SDValues for returning information from TargetLowering to its clients 817 /// that want to combine 818 struct TargetLoweringOpt { 819 SelectionDAG &DAG; 820 bool LegalTys; 821 bool LegalOps; 822 SDValue Old; 823 SDValue New; 824 TargetLoweringOptTargetLoweringOpt825 explicit TargetLoweringOpt(SelectionDAG &InDAG, 826 bool LT, bool LO) : 827 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} 828 LegalTypesTargetLoweringOpt829 bool LegalTypes() const { return LegalTys; } LegalOperationsTargetLoweringOpt830 bool LegalOperations() const { return LegalOps; } 831 CombineToTargetLoweringOpt832 bool CombineTo(SDValue O, SDValue N) { 833 Old = O; 834 New = N; 835 return true; 836 } 837 838 /// ShrinkDemandedConstant - Check to see if the specified operand of the 839 /// specified instruction is a constant integer. If so, check to see if 840 /// there are any bits set in the constant that are not demanded. If so, 841 /// shrink the constant and return true. 842 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded); 843 844 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 845 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 846 /// cast, but it could be generalized for targets with other types of 847 /// implicit widening casts. 848 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 849 DebugLoc dl); 850 }; 851 852 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 853 /// DemandedMask bits of the result of Op are ever used downstream. If we can 854 /// use this information to simplify Op, create a new simplified DAG node and 855 /// return true, returning the original and new nodes in Old and New. 856 /// Otherwise, analyze the expression and return a mask of KnownOne and 857 /// KnownZero bits for the expression (used to simplify the caller). 858 /// The KnownZero/One bits may only be accurate for those bits in the 859 /// DemandedMask. 860 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, 861 APInt &KnownZero, APInt &KnownOne, 862 TargetLoweringOpt &TLO, unsigned Depth = 0) const; 863 864 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in 865 /// Mask are known to be either zero or one and return them in the 866 /// KnownZero/KnownOne bitsets. 867 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 868 const APInt &Mask, 869 APInt &KnownZero, 870 APInt &KnownOne, 871 const SelectionDAG &DAG, 872 unsigned Depth = 0) const; 873 874 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 875 /// targets that want to expose additional information about sign bits to the 876 /// DAG Combiner. 877 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 878 unsigned Depth = 0) const; 879 880 struct DAGCombinerInfo { 881 void *DC; // The DAG Combiner object. 882 bool BeforeLegalize; 883 bool BeforeLegalizeOps; 884 bool CalledByLegalizer; 885 public: 886 SelectionDAG &DAG; 887 DAGCombinerInfoDAGCombinerInfo888 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc) 889 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo), 890 CalledByLegalizer(cl), DAG(dag) {} 891 isBeforeLegalizeDAGCombinerInfo892 bool isBeforeLegalize() const { return BeforeLegalize; } isBeforeLegalizeOpsDAGCombinerInfo893 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; } isCalledByLegalizerDAGCombinerInfo894 bool isCalledByLegalizer() const { return CalledByLegalizer; } 895 896 void AddToWorklist(SDNode *N); 897 void RemoveFromWorklist(SDNode *N); 898 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To, 899 bool AddTo = true); 900 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 901 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 902 903 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 904 }; 905 906 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 907 /// and cc. If it is unable to simplify it, return a null SDValue. 908 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 909 ISD::CondCode Cond, bool foldBooleans, 910 DAGCombinerInfo &DCI, DebugLoc dl) const; 911 912 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 913 /// node is a GlobalAddress + offset. 914 virtual bool 915 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 916 917 /// PerformDAGCombine - This method will be invoked for all target nodes and 918 /// for any target-independent nodes that the target has registered with 919 /// invoke it for. 920 /// 921 /// The semantics are as follows: 922 /// Return Value: 923 /// SDValue.Val == 0 - No change was made 924 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 925 /// otherwise - N should be replaced by the returned Operand. 926 /// 927 /// In addition, methods provided by DAGCombinerInfo may be used to perform 928 /// more complex transformations. 929 /// 930 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 931 932 /// isTypeDesirableForOp - Return true if the target has native support for 933 /// the specified value type and it is 'desirable' to use the type for the 934 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 935 /// instruction encodings are longer and some i16 instructions are slow. isTypeDesirableForOp(unsigned,EVT VT)936 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const { 937 // By default, assume all legal types are desirable. 938 return isTypeLegal(VT); 939 } 940 941 /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner 942 /// to transform a floating point op of specified opcode to a equivalent op of 943 /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM. isDesirableToTransformToIntegerOp(unsigned,EVT)944 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/, 945 EVT /*VT*/) const { 946 return false; 947 } 948 949 /// IsDesirableToPromoteOp - This method query the target whether it is 950 /// beneficial for dag combiner to promote the specified node. If true, it 951 /// should return the desired promotion type by reference. IsDesirableToPromoteOp(SDValue,EVT &)952 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const { 953 return false; 954 } 955 956 //===--------------------------------------------------------------------===// 957 // TargetLowering Configuration Methods - These methods should be invoked by 958 // the derived class constructor to configure this object for the target. 959 // 960 961 protected: 962 /// setBooleanContents - Specify how the target extends the result of a 963 /// boolean value from i1 to a wider type. See getBooleanContents. setBooleanContents(BooleanContent Ty)964 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; } 965 /// setBooleanVectorContents - Specify how the target extends the result 966 /// of a vector boolean value from a vector of i1 to a wider type. See 967 /// getBooleanContents. setBooleanVectorContents(BooleanContent Ty)968 void setBooleanVectorContents(BooleanContent Ty) { 969 BooleanVectorContents = Ty; 970 } 971 972 /// setSchedulingPreference - Specify the target scheduling preference. setSchedulingPreference(Sched::Preference Pref)973 void setSchedulingPreference(Sched::Preference Pref) { 974 SchedPreferenceInfo = Pref; 975 } 976 977 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to 978 /// use _setjmp to implement llvm.setjmp or the non _ version. 979 /// Defaults to false. setUseUnderscoreSetJmp(bool Val)980 void setUseUnderscoreSetJmp(bool Val) { 981 UseUnderscoreSetJmp = Val; 982 } 983 984 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to 985 /// use _longjmp to implement llvm.longjmp or the non _ version. 986 /// Defaults to false. setUseUnderscoreLongJmp(bool Val)987 void setUseUnderscoreLongJmp(bool Val) { 988 UseUnderscoreLongJmp = Val; 989 } 990 991 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this 992 /// specifies the register that llvm.savestack/llvm.restorestack should save 993 /// and restore. setStackPointerRegisterToSaveRestore(unsigned R)994 void setStackPointerRegisterToSaveRestore(unsigned R) { 995 StackPointerRegisterToSaveRestore = R; 996 } 997 998 /// setExceptionPointerRegister - If set to a physical register, this sets 999 /// the register that receives the exception address on entry to a landing 1000 /// pad. setExceptionPointerRegister(unsigned R)1001 void setExceptionPointerRegister(unsigned R) { 1002 ExceptionPointerRegister = R; 1003 } 1004 1005 /// setExceptionSelectorRegister - If set to a physical register, this sets 1006 /// the register that receives the exception typeid on entry to a landing 1007 /// pad. setExceptionSelectorRegister(unsigned R)1008 void setExceptionSelectorRegister(unsigned R) { 1009 ExceptionSelectorRegister = R; 1010 } 1011 1012 /// SelectIsExpensive - Tells the code generator not to expand operations 1013 /// into sequences that use the select operations if possible. 1014 void setSelectIsExpensive(bool isExpensive = true) { 1015 SelectIsExpensive = isExpensive; 1016 } 1017 1018 /// JumpIsExpensive - Tells the code generator not to expand sequence of 1019 /// operations into a separate sequences that increases the amount of 1020 /// flow control. 1021 void setJumpIsExpensive(bool isExpensive = true) { 1022 JumpIsExpensive = isExpensive; 1023 } 1024 1025 /// setIntDivIsCheap - Tells the code generator that integer divide is 1026 /// expensive, and if possible, should be replaced by an alternate sequence 1027 /// of instructions not containing an integer divide. 1028 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } 1029 1030 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate 1031 /// srl/add/sra for a signed divide by power of two, and let the target handle 1032 /// it. 1033 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } 1034 1035 /// addRegisterClass - Add the specified register class as an available 1036 /// regclass for the specified value type. This indicates the selector can 1037 /// handle values of that class natively. addRegisterClass(EVT VT,TargetRegisterClass * RC)1038 void addRegisterClass(EVT VT, TargetRegisterClass *RC) { 1039 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 1040 AvailableRegClasses.push_back(std::make_pair(VT, RC)); 1041 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC; 1042 } 1043 1044 /// findRepresentativeClass - Return the largest legal super-reg register class 1045 /// of the register class for the specified type and its associated "cost". 1046 virtual std::pair<const TargetRegisterClass*, uint8_t> 1047 findRepresentativeClass(EVT VT) const; 1048 1049 /// computeRegisterProperties - Once all of the register classes are added, 1050 /// this allows us to compute derived properties we expose. 1051 void computeRegisterProperties(); 1052 1053 /// setOperationAction - Indicate that the specified operation does not work 1054 /// with the specified type and indicate what to do about it. setOperationAction(unsigned Op,MVT VT,LegalizeAction Action)1055 void setOperationAction(unsigned Op, MVT VT, 1056 LegalizeAction Action) { 1057 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 1058 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action; 1059 } 1060 1061 /// setLoadExtAction - Indicate that the specified load with extension does 1062 /// not work with the specified type and indicate what to do about it. setLoadExtAction(unsigned ExtType,MVT VT,LegalizeAction Action)1063 void setLoadExtAction(unsigned ExtType, MVT VT, 1064 LegalizeAction Action) { 1065 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && 1066 "Table isn't big enough!"); 1067 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; 1068 } 1069 1070 /// setTruncStoreAction - Indicate that the specified truncating store does 1071 /// not work with the specified type and indicate what to do about it. setTruncStoreAction(MVT ValVT,MVT MemVT,LegalizeAction Action)1072 void setTruncStoreAction(MVT ValVT, MVT MemVT, 1073 LegalizeAction Action) { 1074 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE && 1075 "Table isn't big enough!"); 1076 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action; 1077 } 1078 1079 /// setIndexedLoadAction - Indicate that the specified indexed load does or 1080 /// does not work with the specified type and indicate what to do abort 1081 /// it. NOTE: All indexed mode loads are initialized to Expand in 1082 /// TargetLowering.cpp setIndexedLoadAction(unsigned IdxMode,MVT VT,LegalizeAction Action)1083 void setIndexedLoadAction(unsigned IdxMode, MVT VT, 1084 LegalizeAction Action) { 1085 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 1086 (unsigned)Action < 0xf && "Table isn't big enough!"); 1087 // Load action are kept in the upper half. 1088 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0; 1089 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4; 1090 } 1091 1092 /// setIndexedStoreAction - Indicate that the specified indexed store does or 1093 /// does not work with the specified type and indicate what to do about 1094 /// it. NOTE: All indexed mode stores are initialized to Expand in 1095 /// TargetLowering.cpp setIndexedStoreAction(unsigned IdxMode,MVT VT,LegalizeAction Action)1096 void setIndexedStoreAction(unsigned IdxMode, MVT VT, 1097 LegalizeAction Action) { 1098 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE && 1099 (unsigned)Action < 0xf && "Table isn't big enough!"); 1100 // Store action are kept in the lower half. 1101 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f; 1102 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action); 1103 } 1104 1105 /// setCondCodeAction - Indicate that the specified condition code is or isn't 1106 /// supported on the target and indicate what to do about it. setCondCodeAction(ISD::CondCode CC,MVT VT,LegalizeAction Action)1107 void setCondCodeAction(ISD::CondCode CC, MVT VT, 1108 LegalizeAction Action) { 1109 assert(VT < MVT::LAST_VALUETYPE && 1110 (unsigned)CC < array_lengthof(CondCodeActions) && 1111 "Table isn't big enough!"); 1112 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2); 1113 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2; 1114 } 1115 1116 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the 1117 /// promotion code defaults to trying a larger integer/fp until it can find 1118 /// one that works. If that default is insufficient, this method can be used 1119 /// by the target to override the default. AddPromotedToType(unsigned Opc,MVT OrigVT,MVT DestVT)1120 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 1121 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 1122 } 1123 1124 /// setTargetDAGCombine - Targets should invoke this method for each target 1125 /// independent node that they want to provide a custom DAG combiner for by 1126 /// implementing the PerformDAGCombine virtual method. setTargetDAGCombine(ISD::NodeType NT)1127 void setTargetDAGCombine(ISD::NodeType NT) { 1128 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1129 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 1130 } 1131 1132 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in 1133 /// bytes); default is 200 setJumpBufSize(unsigned Size)1134 void setJumpBufSize(unsigned Size) { 1135 JumpBufSize = Size; 1136 } 1137 1138 /// setJumpBufAlignment - Set the target's required jmp_buf buffer 1139 /// alignment (in bytes); default is 0 setJumpBufAlignment(unsigned Align)1140 void setJumpBufAlignment(unsigned Align) { 1141 JumpBufAlignment = Align; 1142 } 1143 1144 /// setMinFunctionAlignment - Set the target's minimum function alignment. setMinFunctionAlignment(unsigned Align)1145 void setMinFunctionAlignment(unsigned Align) { 1146 MinFunctionAlignment = Align; 1147 } 1148 1149 /// setPrefFunctionAlignment - Set the target's preferred function alignment. 1150 /// This should be set if there is a performance benefit to 1151 /// higher-than-minimum alignment setPrefFunctionAlignment(unsigned Align)1152 void setPrefFunctionAlignment(unsigned Align) { 1153 PrefFunctionAlignment = Align; 1154 } 1155 1156 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default 1157 /// alignment is zero, it means the target does not care about loop alignment. setPrefLoopAlignment(unsigned Align)1158 void setPrefLoopAlignment(unsigned Align) { 1159 PrefLoopAlignment = Align; 1160 } 1161 1162 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an 1163 /// argument. setMinStackArgumentAlignment(unsigned Align)1164 void setMinStackArgumentAlignment(unsigned Align) { 1165 MinStackArgumentAlignment = Align; 1166 } 1167 1168 /// setShouldFoldAtomicFences - Set if the target's implementation of the 1169 /// atomic operation intrinsics includes locking. Default is false. setShouldFoldAtomicFences(bool fold)1170 void setShouldFoldAtomicFences(bool fold) { 1171 ShouldFoldAtomicFences = fold; 1172 } 1173 1174 /// setInsertFencesForAtomic - Set if the the DAG builder should 1175 /// automatically insert fences and reduce the order of atomic memory 1176 /// operations to Monotonic. setInsertFencesForAtomic(bool fence)1177 void setInsertFencesForAtomic(bool fence) { 1178 InsertFencesForAtomic = fence; 1179 } 1180 1181 public: 1182 //===--------------------------------------------------------------------===// 1183 // Lowering methods - These methods must be implemented by targets so that 1184 // the SelectionDAGLowering code knows how to lower these. 1185 // 1186 1187 /// LowerFormalArguments - This hook must be implemented to lower the 1188 /// incoming (formal) arguments, described by the Ins array, into the 1189 /// specified DAG. The implementation should fill in the InVals array 1190 /// with legal-type argument values, and return the resulting token 1191 /// chain value. 1192 /// 1193 virtual SDValue LowerFormalArguments(SDValue,CallingConv::ID,bool,const SmallVectorImpl<ISD::InputArg> &,DebugLoc,SelectionDAG &,SmallVectorImpl<SDValue> &)1194 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 1195 bool /*isVarArg*/, 1196 const SmallVectorImpl<ISD::InputArg> &/*Ins*/, 1197 DebugLoc /*dl*/, SelectionDAG &/*DAG*/, 1198 SmallVectorImpl<SDValue> &/*InVals*/) const { 1199 assert(0 && "Not Implemented"); 1200 return SDValue(); // this is here to silence compiler errors 1201 } 1202 1203 /// LowerCallTo - This function lowers an abstract call to a function into an 1204 /// actual call. This returns a pair of operands. The first element is the 1205 /// return value for the function (if RetTy is not VoidTy). The second 1206 /// element is the outgoing token chain. It calls LowerCall to do the actual 1207 /// lowering. 1208 struct ArgListEntry { 1209 SDValue Node; 1210 Type* Ty; 1211 bool isSExt : 1; 1212 bool isZExt : 1; 1213 bool isInReg : 1; 1214 bool isSRet : 1; 1215 bool isNest : 1; 1216 bool isByVal : 1; 1217 uint16_t Alignment; 1218 ArgListEntryArgListEntry1219 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), 1220 isSRet(false), isNest(false), isByVal(false), Alignment(0) { } 1221 }; 1222 typedef std::vector<ArgListEntry> ArgListTy; 1223 std::pair<SDValue, SDValue> 1224 LowerCallTo(SDValue Chain, Type *RetTy, bool RetSExt, bool RetZExt, 1225 bool isVarArg, bool isInreg, unsigned NumFixedArgs, 1226 CallingConv::ID CallConv, bool isTailCall, 1227 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args, 1228 SelectionDAG &DAG, DebugLoc dl) const; 1229 1230 /// LowerCall - This hook must be implemented to lower calls into the 1231 /// the specified DAG. The outgoing arguments to the call are described 1232 /// by the Outs array, and the values to be returned by the call are 1233 /// described by the Ins array. The implementation should fill in the 1234 /// InVals array with legal-type return values from the call, and return 1235 /// the resulting token chain value. 1236 virtual SDValue LowerCall(SDValue,SDValue,CallingConv::ID,bool,bool &,const SmallVectorImpl<ISD::OutputArg> &,const SmallVectorImpl<SDValue> &,const SmallVectorImpl<ISD::InputArg> &,DebugLoc,SelectionDAG &,SmallVectorImpl<SDValue> &)1237 LowerCall(SDValue /*Chain*/, SDValue /*Callee*/, 1238 CallingConv::ID /*CallConv*/, bool /*isVarArg*/, 1239 bool &/*isTailCall*/, 1240 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 1241 const SmallVectorImpl<SDValue> &/*OutVals*/, 1242 const SmallVectorImpl<ISD::InputArg> &/*Ins*/, 1243 DebugLoc /*dl*/, SelectionDAG &/*DAG*/, 1244 SmallVectorImpl<SDValue> &/*InVals*/) const { 1245 assert(0 && "Not Implemented"); 1246 return SDValue(); // this is here to silence compiler errors 1247 } 1248 1249 /// HandleByVal - Target-specific cleanup for formal ByVal parameters. HandleByVal(CCState *,unsigned &)1250 virtual void HandleByVal(CCState *, unsigned &) const {} 1251 1252 /// CanLowerReturn - This hook should be implemented to check whether the 1253 /// return values described by the Outs array can fit into the return 1254 /// registers. If false is returned, an sret-demotion is performed. 1255 /// CanLowerReturn(CallingConv::ID,MachineFunction &,bool,const SmallVectorImpl<ISD::OutputArg> &,LLVMContext &)1256 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/, 1257 MachineFunction &/*MF*/, bool /*isVarArg*/, 1258 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 1259 LLVMContext &/*Context*/) const 1260 { 1261 // Return true by default to get preexisting behavior. 1262 return true; 1263 } 1264 1265 /// LowerReturn - This hook must be implemented to lower outgoing 1266 /// return values, described by the Outs array, into the specified 1267 /// DAG. The implementation should return the resulting token chain 1268 /// value. 1269 /// 1270 virtual SDValue LowerReturn(SDValue,CallingConv::ID,bool,const SmallVectorImpl<ISD::OutputArg> &,const SmallVectorImpl<SDValue> &,DebugLoc,SelectionDAG &)1271 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 1272 bool /*isVarArg*/, 1273 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 1274 const SmallVectorImpl<SDValue> &/*OutVals*/, 1275 DebugLoc /*dl*/, SelectionDAG &/*DAG*/) const { 1276 assert(0 && "Not Implemented"); 1277 return SDValue(); // this is here to silence compiler errors 1278 } 1279 1280 /// isUsedByReturnOnly - Return true if result of the specified node is used 1281 /// by a return node only. This is used to determine whether it is possible 1282 /// to codegen a libcall as tail call at legalization time. isUsedByReturnOnly(SDNode *)1283 virtual bool isUsedByReturnOnly(SDNode *) const { 1284 return false; 1285 } 1286 1287 /// mayBeEmittedAsTailCall - Return true if the target may be able emit the 1288 /// call instruction as a tail call. This is used by optimization passes to 1289 /// determine if it's profitable to duplicate return instructions to enable 1290 /// tailcall optimization. mayBeEmittedAsTailCall(CallInst *)1291 virtual bool mayBeEmittedAsTailCall(CallInst *) const { 1292 return false; 1293 } 1294 1295 /// getTypeForExtArgOrReturn - Return the type that should be used to zero or 1296 /// sign extend a zeroext/signext integer argument or return value. 1297 /// FIXME: Most C calling convention requires the return type to be promoted, 1298 /// but this is not true all the time, e.g. i1 on x86-64. It is also not 1299 /// necessary for non-C calling conventions. The frontend should handle this 1300 /// and include all of the necessary information. getTypeForExtArgOrReturn(LLVMContext & Context,EVT VT,ISD::NodeType)1301 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1302 ISD::NodeType /*ExtendKind*/) const { 1303 EVT MinVT = getRegisterType(Context, MVT::i32); 1304 return VT.bitsLT(MinVT) ? MinVT : VT; 1305 } 1306 1307 /// LowerOperationWrapper - This callback is invoked by the type legalizer 1308 /// to legalize nodes with an illegal operand type but legal result types. 1309 /// It replaces the LowerOperation callback in the type Legalizer. 1310 /// The reason we can not do away with LowerOperation entirely is that 1311 /// LegalizeDAG isn't yet ready to use this callback. 1312 /// TODO: Consider merging with ReplaceNodeResults. 1313 1314 /// The target places new result values for the node in Results (their number 1315 /// and types must exactly match those of the original return values of 1316 /// the node), or leaves Results empty, which indicates that the node is not 1317 /// to be custom lowered after all. 1318 /// The default implementation calls LowerOperation. 1319 virtual void LowerOperationWrapper(SDNode *N, 1320 SmallVectorImpl<SDValue> &Results, 1321 SelectionDAG &DAG) const; 1322 1323 /// LowerOperation - This callback is invoked for operations that are 1324 /// unsupported by the target, which are registered to use 'custom' lowering, 1325 /// and whose defined values are all legal. 1326 /// If the target has no operations that require custom lowering, it need not 1327 /// implement this. The default implementation of this aborts. 1328 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 1329 1330 /// ReplaceNodeResults - This callback is invoked when a node result type is 1331 /// illegal for the target, and the operation was registered to use 'custom' 1332 /// lowering for that result type. The target places new result values for 1333 /// the node in Results (their number and types must exactly match those of 1334 /// the original return values of the node), or leaves Results empty, which 1335 /// indicates that the node is not to be custom lowered after all. 1336 /// 1337 /// If the target has no operations that require custom lowering, it need not 1338 /// implement this. The default implementation aborts. ReplaceNodeResults(SDNode *,SmallVectorImpl<SDValue> &,SelectionDAG &)1339 virtual void ReplaceNodeResults(SDNode * /*N*/, 1340 SmallVectorImpl<SDValue> &/*Results*/, 1341 SelectionDAG &/*DAG*/) const { 1342 assert(0 && "ReplaceNodeResults not implemented for this target!"); 1343 } 1344 1345 /// getTargetNodeName() - This method returns the name of a target specific 1346 /// DAG node. 1347 virtual const char *getTargetNodeName(unsigned Opcode) const; 1348 1349 /// createFastISel - This method returns a target specific FastISel object, 1350 /// or null if the target does not support "fast" ISel. createFastISel(FunctionLoweringInfo &)1351 virtual FastISel *createFastISel(FunctionLoweringInfo &) const { 1352 return 0; 1353 } 1354 1355 //===--------------------------------------------------------------------===// 1356 // Inline Asm Support hooks 1357 // 1358 1359 /// ExpandInlineAsm - This hook allows the target to expand an inline asm 1360 /// call to be explicit llvm code if it wants to. This is useful for 1361 /// turning simple inline asms into LLVM intrinsics, which gives the 1362 /// compiler more information about the behavior of the code. ExpandInlineAsm(CallInst *)1363 virtual bool ExpandInlineAsm(CallInst *) const { 1364 return false; 1365 } 1366 1367 enum ConstraintType { 1368 C_Register, // Constraint represents specific register(s). 1369 C_RegisterClass, // Constraint represents any of register(s) in class. 1370 C_Memory, // Memory constraint. 1371 C_Other, // Something else. 1372 C_Unknown // Unsupported constraint. 1373 }; 1374 1375 enum ConstraintWeight { 1376 // Generic weights. 1377 CW_Invalid = -1, // No match. 1378 CW_Okay = 0, // Acceptable. 1379 CW_Good = 1, // Good weight. 1380 CW_Better = 2, // Better weight. 1381 CW_Best = 3, // Best weight. 1382 1383 // Well-known weights. 1384 CW_SpecificReg = CW_Okay, // Specific register operands. 1385 CW_Register = CW_Good, // Register operands. 1386 CW_Memory = CW_Better, // Memory operands. 1387 CW_Constant = CW_Best, // Constant operand. 1388 CW_Default = CW_Okay // Default or don't know type. 1389 }; 1390 1391 /// AsmOperandInfo - This contains information for each constraint that we are 1392 /// lowering. 1393 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 1394 /// ConstraintCode - This contains the actual string for the code, like "m". 1395 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that 1396 /// most closely matches the operand. 1397 std::string ConstraintCode; 1398 1399 /// ConstraintType - Information about the constraint code, e.g. Register, 1400 /// RegisterClass, Memory, Other, Unknown. 1401 TargetLowering::ConstraintType ConstraintType; 1402 1403 /// CallOperandval - If this is the result output operand or a 1404 /// clobber, this is null, otherwise it is the incoming operand to the 1405 /// CallInst. This gets modified as the asm is processed. 1406 Value *CallOperandVal; 1407 1408 /// ConstraintVT - The ValueType for the operand value. 1409 EVT ConstraintVT; 1410 1411 /// isMatchingInputConstraint - Return true of this is an input operand that 1412 /// is a matching constraint like "4". 1413 bool isMatchingInputConstraint() const; 1414 1415 /// getMatchedOperand - If this is an input matching constraint, this method 1416 /// returns the output operand it matches. 1417 unsigned getMatchedOperand() const; 1418 1419 /// Copy constructor for copying from an AsmOperandInfo. AsmOperandInfoAsmOperandInfo1420 AsmOperandInfo(const AsmOperandInfo &info) 1421 : InlineAsm::ConstraintInfo(info), 1422 ConstraintCode(info.ConstraintCode), 1423 ConstraintType(info.ConstraintType), 1424 CallOperandVal(info.CallOperandVal), 1425 ConstraintVT(info.ConstraintVT) { 1426 } 1427 1428 /// Copy constructor for copying from a ConstraintInfo. AsmOperandInfoAsmOperandInfo1429 AsmOperandInfo(const InlineAsm::ConstraintInfo &info) 1430 : InlineAsm::ConstraintInfo(info), 1431 ConstraintType(TargetLowering::C_Unknown), 1432 CallOperandVal(0), ConstraintVT(MVT::Other) { 1433 } 1434 }; 1435 1436 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector; 1437 1438 /// ParseConstraints - Split up the constraint string from the inline 1439 /// assembly value into the specific constraints and their prefixes, 1440 /// and also tie in the associated operand values. 1441 /// If this returns an empty vector, and if the constraint string itself 1442 /// isn't empty, there was an error parsing. 1443 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const; 1444 1445 /// Examine constraint type and operand type and determine a weight value. 1446 /// The operand object must already have been set up with the operand type. 1447 virtual ConstraintWeight getMultipleConstraintMatchWeight( 1448 AsmOperandInfo &info, int maIndex) const; 1449 1450 /// Examine constraint string and operand type and determine a weight value. 1451 /// The operand object must already have been set up with the operand type. 1452 virtual ConstraintWeight getSingleConstraintMatchWeight( 1453 AsmOperandInfo &info, const char *constraint) const; 1454 1455 /// ComputeConstraintToUse - Determines the constraint code and constraint 1456 /// type to use for the specific AsmOperandInfo, setting 1457 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand 1458 /// being passed in is available, it can be passed in as Op, otherwise an 1459 /// empty SDValue can be passed. 1460 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 1461 SDValue Op, 1462 SelectionDAG *DAG = 0) const; 1463 1464 /// getConstraintType - Given a constraint, return the type of constraint it 1465 /// is for this target. 1466 virtual ConstraintType getConstraintType(const std::string &Constraint) const; 1467 1468 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. 1469 /// {edx}), return the register number and the register class for the 1470 /// register. 1471 /// 1472 /// Given a register class constraint, like 'r', if this corresponds directly 1473 /// to an LLVM register class, return a register of 0 and the register class 1474 /// pointer. 1475 /// 1476 /// This should only be used for C_Register constraints. On error, 1477 /// this returns a register number of 0 and a null register class pointer.. 1478 virtual std::pair<unsigned, const TargetRegisterClass*> 1479 getRegForInlineAsmConstraint(const std::string &Constraint, 1480 EVT VT) const; 1481 1482 /// LowerXConstraint - try to replace an X constraint, which matches anything, 1483 /// with another that has more specific requirements based on the type of the 1484 /// corresponding operand. This returns null if there is no replacement to 1485 /// make. 1486 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 1487 1488 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 1489 /// vector. If it is invalid, don't add anything to Ops. 1490 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 1491 std::vector<SDValue> &Ops, 1492 SelectionDAG &DAG) const; 1493 1494 //===--------------------------------------------------------------------===// 1495 // Instruction Emitting Hooks 1496 // 1497 1498 // EmitInstrWithCustomInserter - This method should be implemented by targets 1499 // that mark instructions with the 'usesCustomInserter' flag. These 1500 // instructions are special in various ways, which require special support to 1501 // insert. The specified MachineInstr is created but not inserted into any 1502 // basic blocks, and this method is called to expand it into a sequence of 1503 // instructions, potentially also creating new basic blocks and control flow. 1504 virtual MachineBasicBlock * 1505 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 1506 1507 /// AdjustInstrPostInstrSelection - This method should be implemented by 1508 /// targets that mark instructions with the 'hasPostISelHook' flag. These 1509 /// instructions must be adjusted after instruction selection by target hooks. 1510 /// e.g. To fill in optional defs for ARM 's' setting instructions. 1511 virtual void 1512 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; 1513 1514 //===--------------------------------------------------------------------===// 1515 // Addressing mode description hooks (used by LSR etc). 1516 // 1517 1518 /// AddrMode - This represents an addressing mode of: 1519 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 1520 /// If BaseGV is null, there is no BaseGV. 1521 /// If BaseOffs is zero, there is no base offset. 1522 /// If HasBaseReg is false, there is no base register. 1523 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 1524 /// no scale. 1525 /// 1526 struct AddrMode { 1527 GlobalValue *BaseGV; 1528 int64_t BaseOffs; 1529 bool HasBaseReg; 1530 int64_t Scale; AddrModeAddrMode1531 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} 1532 }; 1533 1534 /// isLegalAddressingMode - Return true if the addressing mode represented by 1535 /// AM is legal for this target, for a load/store of the specified type. 1536 /// The type may be VoidTy, in which case only return true if the addressing 1537 /// mode is legal for a load/store of any legal type. 1538 /// TODO: Handle pre/postinc as well. 1539 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; 1540 1541 /// isLegalICmpImmediate - Return true if the specified immediate is legal 1542 /// icmp immediate, that is the target has icmp instructions which can compare 1543 /// a register against the immediate without having to materialize the 1544 /// immediate into a register. isLegalICmpImmediate(int64_t)1545 virtual bool isLegalICmpImmediate(int64_t) const { 1546 return true; 1547 } 1548 1549 /// isLegalAddImmediate - Return true if the specified immediate is legal 1550 /// add immediate, that is the target has add instructions which can add 1551 /// a register with the immediate without having to materialize the 1552 /// immediate into a register. isLegalAddImmediate(int64_t)1553 virtual bool isLegalAddImmediate(int64_t) const { 1554 return true; 1555 } 1556 1557 /// isTruncateFree - Return true if it's free to truncate a value of 1558 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1559 /// register EAX to i16 by referencing its sub-register AX. isTruncateFree(Type *,Type *)1560 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const { 1561 return false; 1562 } 1563 isTruncateFree(EVT,EVT)1564 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const { 1565 return false; 1566 } 1567 1568 /// isZExtFree - Return true if any actual instruction that defines a 1569 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result 1570 /// register. This does not necessarily include registers defined in 1571 /// unknown ways, such as incoming arguments, or copies from unknown 1572 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 1573 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 1574 /// all instructions that define 32-bit values implicit zero-extend the 1575 /// result out to 64 bits. isZExtFree(Type *,Type *)1576 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const { 1577 return false; 1578 } 1579 isZExtFree(EVT,EVT)1580 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const { 1581 return false; 1582 } 1583 1584 /// isNarrowingProfitable - Return true if it's profitable to narrow 1585 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 1586 /// from i32 to i8 but not from i32 to i16. isNarrowingProfitable(EVT,EVT)1587 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const { 1588 return false; 1589 } 1590 1591 //===--------------------------------------------------------------------===// 1592 // Div utility functions 1593 // 1594 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, 1595 SelectionDAG &DAG) const; 1596 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, 1597 std::vector<SDNode*>* Created) const; 1598 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, 1599 std::vector<SDNode*>* Created) const; 1600 1601 1602 //===--------------------------------------------------------------------===// 1603 // Runtime Library hooks 1604 // 1605 1606 /// setLibcallName - Rename the default libcall routine name for the specified 1607 /// libcall. setLibcallName(RTLIB::Libcall Call,const char * Name)1608 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 1609 LibcallRoutineNames[Call] = Name; 1610 } 1611 1612 /// getLibcallName - Get the libcall routine name for the specified libcall. 1613 /// getLibcallName(RTLIB::Libcall Call)1614 const char *getLibcallName(RTLIB::Libcall Call) const { 1615 return LibcallRoutineNames[Call]; 1616 } 1617 1618 /// setCmpLibcallCC - Override the default CondCode to be used to test the 1619 /// result of the comparison libcall against zero. setCmpLibcallCC(RTLIB::Libcall Call,ISD::CondCode CC)1620 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 1621 CmpLibcallCCs[Call] = CC; 1622 } 1623 1624 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of 1625 /// the comparison libcall against zero. getCmpLibcallCC(RTLIB::Libcall Call)1626 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 1627 return CmpLibcallCCs[Call]; 1628 } 1629 1630 /// setLibcallCallingConv - Set the CallingConv that should be used for the 1631 /// specified libcall. setLibcallCallingConv(RTLIB::Libcall Call,CallingConv::ID CC)1632 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 1633 LibcallCallingConvs[Call] = CC; 1634 } 1635 1636 /// getLibcallCallingConv - Get the CallingConv that should be used for the 1637 /// specified libcall. getLibcallCallingConv(RTLIB::Libcall Call)1638 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 1639 return LibcallCallingConvs[Call]; 1640 } 1641 1642 private: 1643 const TargetMachine &TM; 1644 const TargetData *TD; 1645 const TargetLoweringObjectFile &TLOF; 1646 1647 /// We are in the process of implementing a new TypeLegalization action 1648 /// which is the promotion of vector elements. This feature is under 1649 /// development. Until this feature is complete, it is only enabled using a 1650 /// flag. We pass this flag using a member because of circular dep issues. 1651 /// This member will be removed with the flag once we complete the transition. 1652 bool mayPromoteElements; 1653 1654 /// PointerTy - The type to use for pointers, usually i32 or i64. 1655 /// 1656 MVT PointerTy; 1657 1658 /// IsLittleEndian - True if this is a little endian target. 1659 /// 1660 bool IsLittleEndian; 1661 1662 /// SelectIsExpensive - Tells the code generator not to expand operations 1663 /// into sequences that use the select operations if possible. 1664 bool SelectIsExpensive; 1665 1666 /// IntDivIsCheap - Tells the code generator not to expand integer divides by 1667 /// constants into a sequence of muls, adds, and shifts. This is a hack until 1668 /// a real cost model is in place. If we ever optimize for size, this will be 1669 /// set to true unconditionally. 1670 bool IntDivIsCheap; 1671 1672 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate 1673 /// srl/add/sra for a signed divide by power of two, and let the target handle 1674 /// it. 1675 bool Pow2DivIsCheap; 1676 1677 /// JumpIsExpensive - Tells the code generator that it shouldn't generate 1678 /// extra flow control instructions and should attempt to combine flow 1679 /// control instructions via predication. 1680 bool JumpIsExpensive; 1681 1682 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement 1683 /// llvm.setjmp. Defaults to false. 1684 bool UseUnderscoreSetJmp; 1685 1686 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement 1687 /// llvm.longjmp. Defaults to false. 1688 bool UseUnderscoreLongJmp; 1689 1690 /// BooleanContents - Information about the contents of the high-bits in 1691 /// boolean values held in a type wider than i1. See getBooleanContents. 1692 BooleanContent BooleanContents; 1693 /// BooleanVectorContents - Information about the contents of the high-bits 1694 /// in boolean vector values when the element type is wider than i1. See 1695 /// getBooleanContents. 1696 BooleanContent BooleanVectorContents; 1697 1698 /// SchedPreferenceInfo - The target scheduling preference: shortest possible 1699 /// total cycles or lowest register usage. 1700 Sched::Preference SchedPreferenceInfo; 1701 1702 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers 1703 unsigned JumpBufSize; 1704 1705 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf 1706 /// buffers 1707 unsigned JumpBufAlignment; 1708 1709 /// MinStackArgumentAlignment - The minimum alignment that any argument 1710 /// on the stack needs to have. 1711 /// 1712 unsigned MinStackArgumentAlignment; 1713 1714 /// MinFunctionAlignment - The minimum function alignment (used when 1715 /// optimizing for size, and to prevent explicitly provided alignment 1716 /// from leading to incorrect code). 1717 /// 1718 unsigned MinFunctionAlignment; 1719 1720 /// PrefFunctionAlignment - The preferred function alignment (used when 1721 /// alignment unspecified and optimizing for speed). 1722 /// 1723 unsigned PrefFunctionAlignment; 1724 1725 /// PrefLoopAlignment - The preferred loop alignment. 1726 /// 1727 unsigned PrefLoopAlignment; 1728 1729 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should 1730 /// be folded into the enclosed atomic intrinsic instruction by the 1731 /// combiner. 1732 bool ShouldFoldAtomicFences; 1733 1734 /// InsertFencesForAtomic - Whether the DAG builder should automatically 1735 /// insert fences and reduce ordering for atomics. (This will be set for 1736 /// for most architectures with weak memory ordering.) 1737 bool InsertFencesForAtomic; 1738 1739 /// StackPointerRegisterToSaveRestore - If set to a physical register, this 1740 /// specifies the register that llvm.savestack/llvm.restorestack should save 1741 /// and restore. 1742 unsigned StackPointerRegisterToSaveRestore; 1743 1744 /// ExceptionPointerRegister - If set to a physical register, this specifies 1745 /// the register that receives the exception address on entry to a landing 1746 /// pad. 1747 unsigned ExceptionPointerRegister; 1748 1749 /// ExceptionSelectorRegister - If set to a physical register, this specifies 1750 /// the register that receives the exception typeid on entry to a landing 1751 /// pad. 1752 unsigned ExceptionSelectorRegister; 1753 1754 /// RegClassForVT - This indicates the default register class to use for 1755 /// each ValueType the target supports natively. 1756 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 1757 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]; 1758 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 1759 1760 /// RepRegClassForVT - This indicates the "representative" register class to 1761 /// use for each ValueType the target supports natively. This information is 1762 /// used by the scheduler to track register pressure. By default, the 1763 /// representative register class is the largest legal super-reg register 1764 /// class of the register class of the specified type. e.g. On x86, i8, i16, 1765 /// and i32's representative class would be GR32. 1766 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE]; 1767 1768 /// RepRegClassCostForVT - This indicates the "cost" of the "representative" 1769 /// register class for each ValueType. The cost is used by the scheduler to 1770 /// approximate register pressure. 1771 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]; 1772 1773 /// TransformToType - For any value types we are promoting or expanding, this 1774 /// contains the value type that we are changing to. For Expanded types, this 1775 /// contains one step of the expand (e.g. i64 -> i32), even if there are 1776 /// multiple steps required (e.g. i64 -> i16). For types natively supported 1777 /// by the system, this holds the same type (e.g. i32 -> i32). 1778 EVT TransformToType[MVT::LAST_VALUETYPE]; 1779 1780 /// OpActions - For each operation and each value type, keep a LegalizeAction 1781 /// that indicates how instruction selection should deal with the operation. 1782 /// Most operations are Legal (aka, supported natively by the target), but 1783 /// operations that are not should be described. Note that operations on 1784 /// non-legal value types are not described here. 1785 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]; 1786 1787 /// LoadExtActions - For each load extension type and each value type, 1788 /// keep a LegalizeAction that indicates how instruction selection should deal 1789 /// with a load of a specific value type and extension type. 1790 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]; 1791 1792 /// TruncStoreActions - For each value type pair keep a LegalizeAction that 1793 /// indicates whether a truncating store of a specific value type and 1794 /// truncating type is legal. 1795 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; 1796 1797 /// IndexedModeActions - For each indexed mode and each value type, 1798 /// keep a pair of LegalizeAction that indicates how instruction 1799 /// selection should deal with the load / store. The first dimension is the 1800 /// value_type for the reference. The second dimension represents the various 1801 /// modes for load store. 1802 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; 1803 1804 /// CondCodeActions - For each condition code (ISD::CondCode) keep a 1805 /// LegalizeAction that indicates how instruction selection should 1806 /// deal with the condition code. 1807 uint64_t CondCodeActions[ISD::SETCC_INVALID]; 1808 1809 ValueTypeActionImpl ValueTypeActions; 1810 1811 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind; 1812 1813 LegalizeKind getTypeConversion(LLVMContext & Context,EVT VT)1814 getTypeConversion(LLVMContext &Context, EVT VT) const { 1815 // If this is a simple type, use the ComputeRegisterProp mechanism. 1816 if (VT.isSimple()) { 1817 assert((unsigned)VT.getSimpleVT().SimpleTy < 1818 array_lengthof(TransformToType)); 1819 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; 1820 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(VT.getSimpleVT()); 1821 1822 assert( 1823 (!(NVT.isSimple() && LA != TypeLegal) || 1824 ValueTypeActions.getTypeAction(NVT.getSimpleVT()) != TypePromoteInteger) 1825 && "Promote may not follow Expand or Promote"); 1826 1827 return LegalizeKind(LA, NVT); 1828 } 1829 1830 // Handle Extended Scalar Types. 1831 if (!VT.isVector()) { 1832 assert(VT.isInteger() && "Float types must be simple"); 1833 unsigned BitSize = VT.getSizeInBits(); 1834 // First promote to a power-of-two size, then expand if necessary. 1835 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 1836 EVT NVT = VT.getRoundIntegerType(Context); 1837 assert(NVT != VT && "Unable to round integer VT"); 1838 LegalizeKind NextStep = getTypeConversion(Context, NVT); 1839 // Avoid multi-step promotion. 1840 if (NextStep.first == TypePromoteInteger) return NextStep; 1841 // Return rounded integer type. 1842 return LegalizeKind(TypePromoteInteger, NVT); 1843 } 1844 1845 return LegalizeKind(TypeExpandInteger, 1846 EVT::getIntegerVT(Context, VT.getSizeInBits()/2)); 1847 } 1848 1849 // Handle vector types. 1850 unsigned NumElts = VT.getVectorNumElements(); 1851 EVT EltVT = VT.getVectorElementType(); 1852 1853 // Vectors with only one element are always scalarized. 1854 if (NumElts == 1) 1855 return LegalizeKind(TypeScalarizeVector, EltVT); 1856 1857 // If we allow the promotion of vector elements using a flag, 1858 // then try to widen vector elements until a legal type is found. 1859 if (mayPromoteElements && EltVT.isInteger()) { 1860 // Vectors with a number of elements that is not a power of two are always 1861 // widened, for example <3 x float> -> <4 x float>. 1862 if (!VT.isPow2VectorType()) { 1863 NumElts = (unsigned)NextPowerOf2(NumElts); 1864 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 1865 return LegalizeKind(TypeWidenVector, NVT); 1866 } 1867 1868 // Examine the element type. 1869 LegalizeKind LK = getTypeConversion(Context, EltVT); 1870 1871 // If type is to be expanded, split the vector. 1872 // <4 x i140> -> <2 x i140> 1873 if (LK.first == TypeExpandInteger) 1874 return LegalizeKind(TypeSplitVector, 1875 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 1876 1877 // Promote the integer element types until a legal vector type is found 1878 // or until the element integer type is too big. If a legal type was not 1879 // found, fallback to the usual mechanism of widening/splitting the 1880 // vector. 1881 while (1) { 1882 // Increase the bitwidth of the element to the next pow-of-two 1883 // (which is greater than 8 bits). 1884 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits() 1885 ).getRoundIntegerType(Context); 1886 1887 // Stop trying when getting a non-simple element type. 1888 // Note that vector elements may be greater than legal vector element 1889 // types. Example: X86 XMM registers hold 64bit element on 32bit systems. 1890 if (!EltVT.isSimple()) break; 1891 1892 // Build a new vector type and check if it is legal. 1893 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1894 // Found a legal promoted vector type. 1895 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 1896 return LegalizeKind(TypePromoteInteger, 1897 EVT::getVectorVT(Context, EltVT, NumElts)); 1898 } 1899 } 1900 1901 // Try to widen the vector until a legal type is found. 1902 // If there is no wider legal type, split the vector. 1903 while (1) { 1904 // Round up to the next power of 2. 1905 NumElts = (unsigned)NextPowerOf2(NumElts); 1906 1907 // If there is no simple vector type with this many elements then there 1908 // cannot be a larger legal vector type. Note that this assumes that 1909 // there are no skipped intermediate vector types in the simple types. 1910 if (!EltVT.isSimple()) break; 1911 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1912 if (LargerVector == MVT()) break; 1913 1914 // If this type is legal then widen the vector. 1915 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 1916 return LegalizeKind(TypeWidenVector, LargerVector); 1917 } 1918 1919 // Widen odd vectors to next power of two. 1920 if (!VT.isPow2VectorType()) { 1921 EVT NVT = VT.getPow2VectorType(Context); 1922 return LegalizeKind(TypeWidenVector, NVT); 1923 } 1924 1925 // Vectors with illegal element types are expanded. 1926 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 1927 return LegalizeKind(TypeSplitVector, NVT); 1928 1929 assert(false && "Unable to handle this kind of vector type"); 1930 return LegalizeKind(TypeLegal, VT); 1931 } 1932 1933 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses; 1934 1935 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would 1936 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(), 1937 /// which sets a bit in this array. 1938 unsigned char 1939 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 1940 1941 /// PromoteToType - For operations that must be promoted to a specific type, 1942 /// this holds the destination type. This map should be sparse, so don't hold 1943 /// it as an array. 1944 /// 1945 /// Targets add entries to this map with AddPromotedToType(..), clients access 1946 /// this with getTypeToPromoteTo(..). 1947 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 1948 PromoteToType; 1949 1950 /// LibcallRoutineNames - Stores the name each libcall. 1951 /// 1952 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]; 1953 1954 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result 1955 /// of each of the comparison libcall against zero. 1956 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 1957 1958 /// LibcallCallingConvs - Stores the CallingConv that should be used for each 1959 /// libcall. 1960 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 1961 1962 protected: 1963 /// When lowering \@llvm.memset this field specifies the maximum number of 1964 /// store operations that may be substituted for the call to memset. Targets 1965 /// must set this value based on the cost threshold for that target. Targets 1966 /// should assume that the memset will be done using as many of the largest 1967 /// store operations first, followed by smaller ones, if necessary, per 1968 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 1969 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 1970 /// store. This only applies to setting a constant array of a constant size. 1971 /// @brief Specify maximum number of store instructions per memset call. 1972 unsigned maxStoresPerMemset; 1973 1974 /// Maximum number of stores operations that may be substituted for the call 1975 /// to memset, used for functions with OptSize attribute. 1976 unsigned maxStoresPerMemsetOptSize; 1977 1978 /// When lowering \@llvm.memcpy this field specifies the maximum number of 1979 /// store operations that may be substituted for a call to memcpy. Targets 1980 /// must set this value based on the cost threshold for that target. Targets 1981 /// should assume that the memcpy will be done using as many of the largest 1982 /// store operations first, followed by smaller ones, if necessary, per 1983 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 1984 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 1985 /// and one 1-byte store. This only applies to copying a constant array of 1986 /// constant size. 1987 /// @brief Specify maximum bytes of store instructions per memcpy call. 1988 unsigned maxStoresPerMemcpy; 1989 1990 /// Maximum number of store operations that may be substituted for a call 1991 /// to memcpy, used for functions with OptSize attribute. 1992 unsigned maxStoresPerMemcpyOptSize; 1993 1994 /// When lowering \@llvm.memmove this field specifies the maximum number of 1995 /// store instructions that may be substituted for a call to memmove. Targets 1996 /// must set this value based on the cost threshold for that target. Targets 1997 /// should assume that the memmove will be done using as many of the largest 1998 /// store operations first, followed by smaller ones, if necessary, per 1999 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 2000 /// with 8-bit alignment would result in nine 1-byte stores. This only 2001 /// applies to copying a constant array of constant size. 2002 /// @brief Specify maximum bytes of store instructions per memmove call. 2003 unsigned maxStoresPerMemmove; 2004 2005 /// Maximum number of store instructions that may be substituted for a call 2006 /// to memmove, used for functions with OpSize attribute. 2007 unsigned maxStoresPerMemmoveOptSize; 2008 2009 /// This field specifies whether the target can benefit from code placement 2010 /// optimization. 2011 bool benefitFromCodePlacementOpt; 2012 2013 private: 2014 /// isLegalRC - Return true if the value types that can be represented by the 2015 /// specified register class are all legal. 2016 bool isLegalRC(const TargetRegisterClass *RC) const; 2017 2018 /// hasLegalSuperRegRegClasses - Return true if the specified register class 2019 /// has one or more super-reg register classes that are legal. 2020 bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const; 2021 }; 2022 2023 /// GetReturnInfo - Given an LLVM IR type and return type attributes, 2024 /// compute the return value EVTs and flags, and optionally also 2025 /// the offsets, if the return value is being lowered to memory. 2026 void GetReturnInfo(Type* ReturnType, Attributes attr, 2027 SmallVectorImpl<ISD::OutputArg> &Outs, 2028 const TargetLowering &TLI, 2029 SmallVectorImpl<uint64_t> *Offsets = 0); 2030 2031 } // end llvm namespace 2032 2033 #endif 2034