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1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Methods common to all machine instructions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Constants.h"
16 #include "llvm/Function.h"
17 #include "llvm/InlineAsm.h"
18 #include "llvm/LLVMContext.h"
19 #include "llvm/Metadata.h"
20 #include "llvm/Module.h"
21 #include "llvm/Type.h"
22 #include "llvm/Value.h"
23 #include "llvm/Assembly/Writer.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCSymbol.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Analysis/AliasAnalysis.h"
36 #include "llvm/Analysis/DebugInfo.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/LeakDetector.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/FoldingSet.h"
43 using namespace llvm;
44 
45 //===----------------------------------------------------------------------===//
46 // MachineOperand Implementation
47 //===----------------------------------------------------------------------===//
48 
49 /// AddRegOperandToRegInfo - Add this register operand to the specified
50 /// MachineRegisterInfo.  If it is null, then the next/prev fields should be
51 /// explicitly nulled out.
AddRegOperandToRegInfo(MachineRegisterInfo * RegInfo)52 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
53   assert(isReg() && "Can only add reg operand to use lists");
54 
55   // If the reginfo pointer is null, just explicitly null out or next/prev
56   // pointers, to ensure they are not garbage.
57   if (RegInfo == 0) {
58     Contents.Reg.Prev = 0;
59     Contents.Reg.Next = 0;
60     return;
61   }
62 
63   // Otherwise, add this operand to the head of the registers use/def list.
64   MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
65 
66   // For SSA values, we prefer to keep the definition at the start of the list.
67   // we do this by skipping over the definition if it is at the head of the
68   // list.
69   if (*Head && (*Head)->isDef())
70     Head = &(*Head)->Contents.Reg.Next;
71 
72   Contents.Reg.Next = *Head;
73   if (Contents.Reg.Next) {
74     assert(getReg() == Contents.Reg.Next->getReg() &&
75            "Different regs on the same list!");
76     Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
77   }
78 
79   Contents.Reg.Prev = Head;
80   *Head = this;
81 }
82 
83 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
84 /// MachineRegisterInfo it is linked with.
RemoveRegOperandFromRegInfo()85 void MachineOperand::RemoveRegOperandFromRegInfo() {
86   assert(isOnRegUseList() && "Reg operand is not on a use list");
87   // Unlink this from the doubly linked list of operands.
88   MachineOperand *NextOp = Contents.Reg.Next;
89   *Contents.Reg.Prev = NextOp;
90   if (NextOp) {
91     assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
92     NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
93   }
94   Contents.Reg.Prev = 0;
95   Contents.Reg.Next = 0;
96 }
97 
setReg(unsigned Reg)98 void MachineOperand::setReg(unsigned Reg) {
99   if (getReg() == Reg) return; // No change.
100 
101   // Otherwise, we have to change the register.  If this operand is embedded
102   // into a machine function, we need to update the old and new register's
103   // use/def lists.
104   if (MachineInstr *MI = getParent())
105     if (MachineBasicBlock *MBB = MI->getParent())
106       if (MachineFunction *MF = MBB->getParent()) {
107         RemoveRegOperandFromRegInfo();
108         SmallContents.RegNo = Reg;
109         AddRegOperandToRegInfo(&MF->getRegInfo());
110         return;
111       }
112 
113   // Otherwise, just change the register, no problem.  :)
114   SmallContents.RegNo = Reg;
115 }
116 
substVirtReg(unsigned Reg,unsigned SubIdx,const TargetRegisterInfo & TRI)117 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
118                                   const TargetRegisterInfo &TRI) {
119   assert(TargetRegisterInfo::isVirtualRegister(Reg));
120   if (SubIdx && getSubReg())
121     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
122   setReg(Reg);
123   if (SubIdx)
124     setSubReg(SubIdx);
125 }
126 
substPhysReg(unsigned Reg,const TargetRegisterInfo & TRI)127 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
128   assert(TargetRegisterInfo::isPhysicalRegister(Reg));
129   if (getSubReg()) {
130     Reg = TRI.getSubReg(Reg, getSubReg());
131     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
132     // That won't happen in legal code.
133     setSubReg(0);
134   }
135   setReg(Reg);
136 }
137 
138 /// ChangeToImmediate - Replace this operand with a new immediate operand of
139 /// the specified value.  If an operand is known to be an immediate already,
140 /// the setImm method should be used.
ChangeToImmediate(int64_t ImmVal)141 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
142   // If this operand is currently a register operand, and if this is in a
143   // function, deregister the operand from the register's use/def list.
144   if (isReg() && getParent() && getParent()->getParent() &&
145       getParent()->getParent()->getParent())
146     RemoveRegOperandFromRegInfo();
147 
148   OpKind = MO_Immediate;
149   Contents.ImmVal = ImmVal;
150 }
151 
152 /// ChangeToRegister - Replace this operand with a new register operand of
153 /// the specified value.  If an operand is known to be an register already,
154 /// the setReg method should be used.
ChangeToRegister(unsigned Reg,bool isDef,bool isImp,bool isKill,bool isDead,bool isUndef,bool isDebug)155 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
156                                       bool isKill, bool isDead, bool isUndef,
157                                       bool isDebug) {
158   // If this operand is already a register operand, use setReg to update the
159   // register's use/def lists.
160   if (isReg()) {
161     assert(!isEarlyClobber());
162     setReg(Reg);
163   } else {
164     // Otherwise, change this to a register and set the reg#.
165     OpKind = MO_Register;
166     SmallContents.RegNo = Reg;
167 
168     // If this operand is embedded in a function, add the operand to the
169     // register's use/def list.
170     if (MachineInstr *MI = getParent())
171       if (MachineBasicBlock *MBB = MI->getParent())
172         if (MachineFunction *MF = MBB->getParent())
173           AddRegOperandToRegInfo(&MF->getRegInfo());
174   }
175 
176   IsDef = isDef;
177   IsImp = isImp;
178   IsKill = isKill;
179   IsDead = isDead;
180   IsUndef = isUndef;
181   IsEarlyClobber = false;
182   IsDebug = isDebug;
183   SubReg = 0;
184 }
185 
186 /// isIdenticalTo - Return true if this operand is identical to the specified
187 /// operand.
isIdenticalTo(const MachineOperand & Other) const188 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
189   if (getType() != Other.getType() ||
190       getTargetFlags() != Other.getTargetFlags())
191     return false;
192 
193   switch (getType()) {
194   default: llvm_unreachable("Unrecognized operand type");
195   case MachineOperand::MO_Register:
196     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
197            getSubReg() == Other.getSubReg();
198   case MachineOperand::MO_Immediate:
199     return getImm() == Other.getImm();
200   case MachineOperand::MO_CImmediate:
201     return getCImm() == Other.getCImm();
202   case MachineOperand::MO_FPImmediate:
203     return getFPImm() == Other.getFPImm();
204   case MachineOperand::MO_MachineBasicBlock:
205     return getMBB() == Other.getMBB();
206   case MachineOperand::MO_FrameIndex:
207     return getIndex() == Other.getIndex();
208   case MachineOperand::MO_ConstantPoolIndex:
209     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
210   case MachineOperand::MO_JumpTableIndex:
211     return getIndex() == Other.getIndex();
212   case MachineOperand::MO_GlobalAddress:
213     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
214   case MachineOperand::MO_ExternalSymbol:
215     return !strcmp(getSymbolName(), Other.getSymbolName()) &&
216            getOffset() == Other.getOffset();
217   case MachineOperand::MO_BlockAddress:
218     return getBlockAddress() == Other.getBlockAddress();
219   case MachineOperand::MO_MCSymbol:
220     return getMCSymbol() == Other.getMCSymbol();
221   case MachineOperand::MO_Metadata:
222     return getMetadata() == Other.getMetadata();
223   }
224 }
225 
226 /// print - Print the specified machine operand.
227 ///
print(raw_ostream & OS,const TargetMachine * TM) const228 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
229   // If the instruction is embedded into a basic block, we can find the
230   // target info for the instruction.
231   if (!TM)
232     if (const MachineInstr *MI = getParent())
233       if (const MachineBasicBlock *MBB = MI->getParent())
234         if (const MachineFunction *MF = MBB->getParent())
235           TM = &MF->getTarget();
236   const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
237 
238   switch (getType()) {
239   case MachineOperand::MO_Register:
240     OS << PrintReg(getReg(), TRI, getSubReg());
241 
242     if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
243         isEarlyClobber()) {
244       OS << '<';
245       bool NeedComma = false;
246       if (isDef()) {
247         if (NeedComma) OS << ',';
248         if (isEarlyClobber())
249           OS << "earlyclobber,";
250         if (isImplicit())
251           OS << "imp-";
252         OS << "def";
253         NeedComma = true;
254       } else if (isImplicit()) {
255           OS << "imp-use";
256           NeedComma = true;
257       }
258 
259       if (isKill() || isDead() || isUndef()) {
260         if (NeedComma) OS << ',';
261         if (isKill())  OS << "kill";
262         if (isDead())  OS << "dead";
263         if (isUndef()) {
264           if (isKill() || isDead())
265             OS << ',';
266           OS << "undef";
267         }
268       }
269       OS << '>';
270     }
271     break;
272   case MachineOperand::MO_Immediate:
273     OS << getImm();
274     break;
275   case MachineOperand::MO_CImmediate:
276     getCImm()->getValue().print(OS, false);
277     break;
278   case MachineOperand::MO_FPImmediate:
279     if (getFPImm()->getType()->isFloatTy())
280       OS << getFPImm()->getValueAPF().convertToFloat();
281     else
282       OS << getFPImm()->getValueAPF().convertToDouble();
283     break;
284   case MachineOperand::MO_MachineBasicBlock:
285     OS << "<BB#" << getMBB()->getNumber() << ">";
286     break;
287   case MachineOperand::MO_FrameIndex:
288     OS << "<fi#" << getIndex() << '>';
289     break;
290   case MachineOperand::MO_ConstantPoolIndex:
291     OS << "<cp#" << getIndex();
292     if (getOffset()) OS << "+" << getOffset();
293     OS << '>';
294     break;
295   case MachineOperand::MO_JumpTableIndex:
296     OS << "<jt#" << getIndex() << '>';
297     break;
298   case MachineOperand::MO_GlobalAddress:
299     OS << "<ga:";
300     WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
301     if (getOffset()) OS << "+" << getOffset();
302     OS << '>';
303     break;
304   case MachineOperand::MO_ExternalSymbol:
305     OS << "<es:" << getSymbolName();
306     if (getOffset()) OS << "+" << getOffset();
307     OS << '>';
308     break;
309   case MachineOperand::MO_BlockAddress:
310     OS << '<';
311     WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
312     OS << '>';
313     break;
314   case MachineOperand::MO_Metadata:
315     OS << '<';
316     WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
317     OS << '>';
318     break;
319   case MachineOperand::MO_MCSymbol:
320     OS << "<MCSym=" << *getMCSymbol() << '>';
321     break;
322   default:
323     llvm_unreachable("Unrecognized operand type");
324   }
325 
326   if (unsigned TF = getTargetFlags())
327     OS << "[TF=" << TF << ']';
328 }
329 
330 //===----------------------------------------------------------------------===//
331 // MachineMemOperand Implementation
332 //===----------------------------------------------------------------------===//
333 
334 /// getAddrSpace - Return the LLVM IR address space number that this pointer
335 /// points into.
getAddrSpace() const336 unsigned MachinePointerInfo::getAddrSpace() const {
337   if (V == 0) return 0;
338   return cast<PointerType>(V->getType())->getAddressSpace();
339 }
340 
341 /// getConstantPool - Return a MachinePointerInfo record that refers to the
342 /// constant pool.
getConstantPool()343 MachinePointerInfo MachinePointerInfo::getConstantPool() {
344   return MachinePointerInfo(PseudoSourceValue::getConstantPool());
345 }
346 
347 /// getFixedStack - Return a MachinePointerInfo record that refers to the
348 /// the specified FrameIndex.
getFixedStack(int FI,int64_t offset)349 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
350   return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
351 }
352 
getJumpTable()353 MachinePointerInfo MachinePointerInfo::getJumpTable() {
354   return MachinePointerInfo(PseudoSourceValue::getJumpTable());
355 }
356 
getGOT()357 MachinePointerInfo MachinePointerInfo::getGOT() {
358   return MachinePointerInfo(PseudoSourceValue::getGOT());
359 }
360 
getStack(int64_t Offset)361 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
362   return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
363 }
364 
MachineMemOperand(MachinePointerInfo ptrinfo,unsigned f,uint64_t s,unsigned int a,const MDNode * TBAAInfo)365 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
366                                      uint64_t s, unsigned int a,
367                                      const MDNode *TBAAInfo)
368   : PtrInfo(ptrinfo), Size(s),
369     Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
370     TBAAInfo(TBAAInfo) {
371   assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
372          "invalid pointer value");
373   assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
374   assert((isLoad() || isStore()) && "Not a load/store!");
375 }
376 
377 /// Profile - Gather unique data for the object.
378 ///
Profile(FoldingSetNodeID & ID) const379 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
380   ID.AddInteger(getOffset());
381   ID.AddInteger(Size);
382   ID.AddPointer(getValue());
383   ID.AddInteger(Flags);
384 }
385 
refineAlignment(const MachineMemOperand * MMO)386 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
387   // The Value and Offset may differ due to CSE. But the flags and size
388   // should be the same.
389   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
390   assert(MMO->getSize() == getSize() && "Size mismatch!");
391 
392   if (MMO->getBaseAlignment() >= getBaseAlignment()) {
393     // Update the alignment value.
394     Flags = (Flags & ((1 << MOMaxBits) - 1)) |
395       ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
396     // Also update the base and offset, because the new alignment may
397     // not be applicable with the old ones.
398     PtrInfo = MMO->PtrInfo;
399   }
400 }
401 
402 /// getAlignment - Return the minimum known alignment in bytes of the
403 /// actual memory reference.
getAlignment() const404 uint64_t MachineMemOperand::getAlignment() const {
405   return MinAlign(getBaseAlignment(), getOffset());
406 }
407 
operator <<(raw_ostream & OS,const MachineMemOperand & MMO)408 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
409   assert((MMO.isLoad() || MMO.isStore()) &&
410          "SV has to be a load, store or both.");
411 
412   if (MMO.isVolatile())
413     OS << "Volatile ";
414 
415   if (MMO.isLoad())
416     OS << "LD";
417   if (MMO.isStore())
418     OS << "ST";
419   OS << MMO.getSize();
420 
421   // Print the address information.
422   OS << "[";
423   if (!MMO.getValue())
424     OS << "<unknown>";
425   else
426     WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
427 
428   // If the alignment of the memory reference itself differs from the alignment
429   // of the base pointer, print the base alignment explicitly, next to the base
430   // pointer.
431   if (MMO.getBaseAlignment() != MMO.getAlignment())
432     OS << "(align=" << MMO.getBaseAlignment() << ")";
433 
434   if (MMO.getOffset() != 0)
435     OS << "+" << MMO.getOffset();
436   OS << "]";
437 
438   // Print the alignment of the reference.
439   if (MMO.getBaseAlignment() != MMO.getAlignment() ||
440       MMO.getBaseAlignment() != MMO.getSize())
441     OS << "(align=" << MMO.getAlignment() << ")";
442 
443   // Print TBAA info.
444   if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
445     OS << "(tbaa=";
446     if (TBAAInfo->getNumOperands() > 0)
447       WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
448     else
449       OS << "<unknown>";
450     OS << ")";
451   }
452 
453   // Print nontemporal info.
454   if (MMO.isNonTemporal())
455     OS << "(nontemporal)";
456 
457   return OS;
458 }
459 
460 //===----------------------------------------------------------------------===//
461 // MachineInstr Implementation
462 //===----------------------------------------------------------------------===//
463 
464 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
465 /// MCID NULL and no operands.
MachineInstr()466 MachineInstr::MachineInstr()
467   : MCID(0), Flags(0), AsmPrinterFlags(0),
468     MemRefs(0), MemRefsEnd(0),
469     Parent(0) {
470   // Make sure that we get added to a machine basicblock
471   LeakDetector::addGarbageObject(this);
472 }
473 
addImplicitDefUseOperands()474 void MachineInstr::addImplicitDefUseOperands() {
475   if (MCID->ImplicitDefs)
476     for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs)
477       addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
478   if (MCID->ImplicitUses)
479     for (const unsigned *ImpUses = MCID->ImplicitUses; *ImpUses; ++ImpUses)
480       addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
481 }
482 
483 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
484 /// implicit operands. It reserves space for the number of operands specified by
485 /// the MCInstrDesc.
MachineInstr(const MCInstrDesc & tid,bool NoImp)486 MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
487   : MCID(&tid), Flags(0), AsmPrinterFlags(0),
488     MemRefs(0), MemRefsEnd(0), Parent(0) {
489   unsigned NumImplicitOps = 0;
490   if (!NoImp)
491     NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
492   Operands.reserve(NumImplicitOps + MCID->getNumOperands());
493   if (!NoImp)
494     addImplicitDefUseOperands();
495   // Make sure that we get added to a machine basicblock
496   LeakDetector::addGarbageObject(this);
497 }
498 
499 /// MachineInstr ctor - As above, but with a DebugLoc.
MachineInstr(const MCInstrDesc & tid,const DebugLoc dl,bool NoImp)500 MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
501                            bool NoImp)
502   : MCID(&tid), Flags(0), AsmPrinterFlags(0),
503     MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
504   unsigned NumImplicitOps = 0;
505   if (!NoImp)
506     NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
507   Operands.reserve(NumImplicitOps + MCID->getNumOperands());
508   if (!NoImp)
509     addImplicitDefUseOperands();
510   // Make sure that we get added to a machine basicblock
511   LeakDetector::addGarbageObject(this);
512 }
513 
514 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
515 /// that the MachineInstr is created and added to the end of the specified
516 /// basic block.
MachineInstr(MachineBasicBlock * MBB,const MCInstrDesc & tid)517 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
518   : MCID(&tid), Flags(0), AsmPrinterFlags(0),
519     MemRefs(0), MemRefsEnd(0), Parent(0) {
520   assert(MBB && "Cannot use inserting ctor with null basic block!");
521   unsigned NumImplicitOps =
522     MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
523   Operands.reserve(NumImplicitOps + MCID->getNumOperands());
524   addImplicitDefUseOperands();
525   // Make sure that we get added to a machine basicblock
526   LeakDetector::addGarbageObject(this);
527   MBB->push_back(this);  // Add instruction to end of basic block!
528 }
529 
530 /// MachineInstr ctor - As above, but with a DebugLoc.
531 ///
MachineInstr(MachineBasicBlock * MBB,const DebugLoc dl,const MCInstrDesc & tid)532 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
533                            const MCInstrDesc &tid)
534   : MCID(&tid), Flags(0), AsmPrinterFlags(0),
535     MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
536   assert(MBB && "Cannot use inserting ctor with null basic block!");
537   unsigned NumImplicitOps =
538     MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
539   Operands.reserve(NumImplicitOps + MCID->getNumOperands());
540   addImplicitDefUseOperands();
541   // Make sure that we get added to a machine basicblock
542   LeakDetector::addGarbageObject(this);
543   MBB->push_back(this);  // Add instruction to end of basic block!
544 }
545 
546 /// MachineInstr ctor - Copies MachineInstr arg exactly
547 ///
MachineInstr(MachineFunction & MF,const MachineInstr & MI)548 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
549   : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
550     MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
551     Parent(0), debugLoc(MI.getDebugLoc()) {
552   Operands.reserve(MI.getNumOperands());
553 
554   // Add operands
555   for (unsigned i = 0; i != MI.getNumOperands(); ++i)
556     addOperand(MI.getOperand(i));
557 
558   // Copy all the flags.
559   Flags = MI.Flags;
560 
561   // Set parent to null.
562   Parent = 0;
563 
564   LeakDetector::addGarbageObject(this);
565 }
566 
~MachineInstr()567 MachineInstr::~MachineInstr() {
568   LeakDetector::removeGarbageObject(this);
569 #ifndef NDEBUG
570   for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
571     assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
572     assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
573            "Reg operand def/use list corrupted");
574   }
575 #endif
576 }
577 
578 /// getRegInfo - If this instruction is embedded into a MachineFunction,
579 /// return the MachineRegisterInfo object for the current function, otherwise
580 /// return null.
getRegInfo()581 MachineRegisterInfo *MachineInstr::getRegInfo() {
582   if (MachineBasicBlock *MBB = getParent())
583     return &MBB->getParent()->getRegInfo();
584   return 0;
585 }
586 
587 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
588 /// this instruction from their respective use lists.  This requires that the
589 /// operands already be on their use lists.
RemoveRegOperandsFromUseLists()590 void MachineInstr::RemoveRegOperandsFromUseLists() {
591   for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
592     if (Operands[i].isReg())
593       Operands[i].RemoveRegOperandFromRegInfo();
594   }
595 }
596 
597 /// AddRegOperandsToUseLists - Add all of the register operands in
598 /// this instruction from their respective use lists.  This requires that the
599 /// operands not be on their use lists yet.
AddRegOperandsToUseLists(MachineRegisterInfo & RegInfo)600 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
601   for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
602     if (Operands[i].isReg())
603       Operands[i].AddRegOperandToRegInfo(&RegInfo);
604   }
605 }
606 
607 
608 /// addOperand - Add the specified operand to the instruction.  If it is an
609 /// implicit operand, it is added to the end of the operand list.  If it is
610 /// an explicit operand it is added at the end of the explicit operand list
611 /// (before the first implicit operand).
addOperand(const MachineOperand & Op)612 void MachineInstr::addOperand(const MachineOperand &Op) {
613   assert(MCID && "Cannot add operands before providing an instr descriptor");
614   bool isImpReg = Op.isReg() && Op.isImplicit();
615   MachineRegisterInfo *RegInfo = getRegInfo();
616 
617   // If the Operands backing store is reallocated, all register operands must
618   // be removed and re-added to RegInfo.  It is storing pointers to operands.
619   bool Reallocate = RegInfo &&
620     !Operands.empty() && Operands.size() == Operands.capacity();
621 
622   // Find the insert location for the new operand.  Implicit registers go at
623   // the end, everything goes before the implicit regs.
624   unsigned OpNo = Operands.size();
625 
626   // Remove all the implicit operands from RegInfo if they need to be shifted.
627   // FIXME: Allow mixed explicit and implicit operands on inline asm.
628   // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
629   // implicit-defs, but they must not be moved around.  See the FIXME in
630   // InstrEmitter.cpp.
631   if (!isImpReg && !isInlineAsm()) {
632     while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
633       --OpNo;
634       if (RegInfo)
635         Operands[OpNo].RemoveRegOperandFromRegInfo();
636     }
637   }
638 
639   // OpNo now points as the desired insertion point.  Unless this is a variadic
640   // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
641   assert((isImpReg || MCID->isVariadic() || OpNo < MCID->getNumOperands()) &&
642          "Trying to add an operand to a machine instr that is already done!");
643 
644   // All operands from OpNo have been removed from RegInfo.  If the Operands
645   // backing store needs to be reallocated, we also need to remove any other
646   // register operands.
647   if (Reallocate)
648     for (unsigned i = 0; i != OpNo; ++i)
649       if (Operands[i].isReg())
650         Operands[i].RemoveRegOperandFromRegInfo();
651 
652   // Insert the new operand at OpNo.
653   Operands.insert(Operands.begin() + OpNo, Op);
654   Operands[OpNo].ParentMI = this;
655 
656   // The Operands backing store has now been reallocated, so we can re-add the
657   // operands before OpNo.
658   if (Reallocate)
659     for (unsigned i = 0; i != OpNo; ++i)
660       if (Operands[i].isReg())
661         Operands[i].AddRegOperandToRegInfo(RegInfo);
662 
663   // When adding a register operand, tell RegInfo about it.
664   if (Operands[OpNo].isReg()) {
665     // Add the new operand to RegInfo, even when RegInfo is NULL.
666     // This will initialize the linked list pointers.
667     Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
668     // If the register operand is flagged as early, mark the operand as such.
669     if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
670       Operands[OpNo].setIsEarlyClobber(true);
671   }
672 
673   // Re-add all the implicit ops.
674   if (RegInfo) {
675     for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
676       assert(Operands[i].isReg() && "Should only be an implicit reg!");
677       Operands[i].AddRegOperandToRegInfo(RegInfo);
678     }
679   }
680 }
681 
682 /// RemoveOperand - Erase an operand  from an instruction, leaving it with one
683 /// fewer operand than it started with.
684 ///
RemoveOperand(unsigned OpNo)685 void MachineInstr::RemoveOperand(unsigned OpNo) {
686   assert(OpNo < Operands.size() && "Invalid operand number");
687 
688   // Special case removing the last one.
689   if (OpNo == Operands.size()-1) {
690     // If needed, remove from the reg def/use list.
691     if (Operands.back().isReg() && Operands.back().isOnRegUseList())
692       Operands.back().RemoveRegOperandFromRegInfo();
693 
694     Operands.pop_back();
695     return;
696   }
697 
698   // Otherwise, we are removing an interior operand.  If we have reginfo to
699   // update, remove all operands that will be shifted down from their reg lists,
700   // move everything down, then re-add them.
701   MachineRegisterInfo *RegInfo = getRegInfo();
702   if (RegInfo) {
703     for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
704       if (Operands[i].isReg())
705         Operands[i].RemoveRegOperandFromRegInfo();
706     }
707   }
708 
709   Operands.erase(Operands.begin()+OpNo);
710 
711   if (RegInfo) {
712     for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
713       if (Operands[i].isReg())
714         Operands[i].AddRegOperandToRegInfo(RegInfo);
715     }
716   }
717 }
718 
719 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
720 /// This function should be used only occasionally. The setMemRefs function
721 /// is the primary method for setting up a MachineInstr's MemRefs list.
addMemOperand(MachineFunction & MF,MachineMemOperand * MO)722 void MachineInstr::addMemOperand(MachineFunction &MF,
723                                  MachineMemOperand *MO) {
724   mmo_iterator OldMemRefs = MemRefs;
725   mmo_iterator OldMemRefsEnd = MemRefsEnd;
726 
727   size_t NewNum = (MemRefsEnd - MemRefs) + 1;
728   mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
729   mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
730 
731   std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
732   NewMemRefs[NewNum - 1] = MO;
733 
734   MemRefs = NewMemRefs;
735   MemRefsEnd = NewMemRefsEnd;
736 }
737 
isIdenticalTo(const MachineInstr * Other,MICheckType Check) const738 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
739                                  MICheckType Check) const {
740   // If opcodes or number of operands are not the same then the two
741   // instructions are obviously not identical.
742   if (Other->getOpcode() != getOpcode() ||
743       Other->getNumOperands() != getNumOperands())
744     return false;
745 
746   // Check operands to make sure they match.
747   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
748     const MachineOperand &MO = getOperand(i);
749     const MachineOperand &OMO = Other->getOperand(i);
750     if (!MO.isReg()) {
751       if (!MO.isIdenticalTo(OMO))
752         return false;
753       continue;
754     }
755 
756     // Clients may or may not want to ignore defs when testing for equality.
757     // For example, machine CSE pass only cares about finding common
758     // subexpressions, so it's safe to ignore virtual register defs.
759     if (MO.isDef()) {
760       if (Check == IgnoreDefs)
761         continue;
762       else if (Check == IgnoreVRegDefs) {
763         if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
764             TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
765           if (MO.getReg() != OMO.getReg())
766             return false;
767       } else {
768         if (!MO.isIdenticalTo(OMO))
769           return false;
770         if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
771           return false;
772       }
773     } else {
774       if (!MO.isIdenticalTo(OMO))
775         return false;
776       if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
777         return false;
778     }
779   }
780   // If DebugLoc does not match then two dbg.values are not identical.
781   if (isDebugValue())
782     if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
783         && getDebugLoc() != Other->getDebugLoc())
784       return false;
785   return true;
786 }
787 
788 /// removeFromParent - This method unlinks 'this' from the containing basic
789 /// block, and returns it, but does not delete it.
removeFromParent()790 MachineInstr *MachineInstr::removeFromParent() {
791   assert(getParent() && "Not embedded in a basic block!");
792   getParent()->remove(this);
793   return this;
794 }
795 
796 
797 /// eraseFromParent - This method unlinks 'this' from the containing basic
798 /// block, and deletes it.
eraseFromParent()799 void MachineInstr::eraseFromParent() {
800   assert(getParent() && "Not embedded in a basic block!");
801   getParent()->erase(this);
802 }
803 
804 
805 /// getNumExplicitOperands - Returns the number of non-implicit operands.
806 ///
getNumExplicitOperands() const807 unsigned MachineInstr::getNumExplicitOperands() const {
808   unsigned NumOperands = MCID->getNumOperands();
809   if (!MCID->isVariadic())
810     return NumOperands;
811 
812   for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
813     const MachineOperand &MO = getOperand(i);
814     if (!MO.isReg() || !MO.isImplicit())
815       NumOperands++;
816   }
817   return NumOperands;
818 }
819 
isStackAligningInlineAsm() const820 bool MachineInstr::isStackAligningInlineAsm() const {
821   if (isInlineAsm()) {
822     unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
823     if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
824       return true;
825   }
826   return false;
827 }
828 
findInlineAsmFlagIdx(unsigned OpIdx,unsigned * GroupNo) const829 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
830                                        unsigned *GroupNo) const {
831   assert(isInlineAsm() && "Expected an inline asm instruction");
832   assert(OpIdx < getNumOperands() && "OpIdx out of range");
833 
834   // Ignore queries about the initial operands.
835   if (OpIdx < InlineAsm::MIOp_FirstOperand)
836     return -1;
837 
838   unsigned Group = 0;
839   unsigned NumOps;
840   for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
841        i += NumOps) {
842     const MachineOperand &FlagMO = getOperand(i);
843     // If we reach the implicit register operands, stop looking.
844     if (!FlagMO.isImm())
845       return -1;
846     NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
847     if (i + NumOps > OpIdx) {
848       if (GroupNo)
849         *GroupNo = Group;
850       return i;
851     }
852     ++Group;
853   }
854   return -1;
855 }
856 
857 const TargetRegisterClass*
getRegClassConstraint(unsigned OpIdx,const TargetInstrInfo * TII,const TargetRegisterInfo * TRI) const858 MachineInstr::getRegClassConstraint(unsigned OpIdx,
859                                     const TargetInstrInfo *TII,
860                                     const TargetRegisterInfo *TRI) const {
861   // Most opcodes have fixed constraints in their MCInstrDesc.
862   if (!isInlineAsm())
863     return TII->getRegClass(getDesc(), OpIdx, TRI);
864 
865   if (!getOperand(OpIdx).isReg())
866     return NULL;
867 
868   // For tied uses on inline asm, get the constraint from the def.
869   unsigned DefIdx;
870   if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
871     OpIdx = DefIdx;
872 
873   // Inline asm stores register class constraints in the flag word.
874   int FlagIdx = findInlineAsmFlagIdx(OpIdx);
875   if (FlagIdx < 0)
876     return NULL;
877 
878   unsigned Flag = getOperand(FlagIdx).getImm();
879   unsigned RCID;
880   if (InlineAsm::hasRegClassConstraint(Flag, RCID))
881     return TRI->getRegClass(RCID);
882 
883   // Assume that all registers in a memory operand are pointers.
884   if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
885     return TRI->getPointerRegClass();
886 
887   return NULL;
888 }
889 
890 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
891 /// the specific register or -1 if it is not found. It further tightens
892 /// the search criteria to a use that kills the register if isKill is true.
findRegisterUseOperandIdx(unsigned Reg,bool isKill,const TargetRegisterInfo * TRI) const893 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
894                                           const TargetRegisterInfo *TRI) const {
895   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
896     const MachineOperand &MO = getOperand(i);
897     if (!MO.isReg() || !MO.isUse())
898       continue;
899     unsigned MOReg = MO.getReg();
900     if (!MOReg)
901       continue;
902     if (MOReg == Reg ||
903         (TRI &&
904          TargetRegisterInfo::isPhysicalRegister(MOReg) &&
905          TargetRegisterInfo::isPhysicalRegister(Reg) &&
906          TRI->isSubRegister(MOReg, Reg)))
907       if (!isKill || MO.isKill())
908         return i;
909   }
910   return -1;
911 }
912 
913 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
914 /// indicating if this instruction reads or writes Reg. This also considers
915 /// partial defines.
916 std::pair<bool,bool>
readsWritesVirtualRegister(unsigned Reg,SmallVectorImpl<unsigned> * Ops) const917 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
918                                          SmallVectorImpl<unsigned> *Ops) const {
919   bool PartDef = false; // Partial redefine.
920   bool FullDef = false; // Full define.
921   bool Use = false;
922 
923   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
924     const MachineOperand &MO = getOperand(i);
925     if (!MO.isReg() || MO.getReg() != Reg)
926       continue;
927     if (Ops)
928       Ops->push_back(i);
929     if (MO.isUse())
930       Use |= !MO.isUndef();
931     else if (MO.getSubReg() && !MO.isUndef())
932       // A partial <def,undef> doesn't count as reading the register.
933       PartDef = true;
934     else
935       FullDef = true;
936   }
937   // A partial redefine uses Reg unless there is also a full define.
938   return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
939 }
940 
941 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
942 /// the specified register or -1 if it is not found. If isDead is true, defs
943 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
944 /// also checks if there is a def of a super-register.
945 int
findRegisterDefOperandIdx(unsigned Reg,bool isDead,bool Overlap,const TargetRegisterInfo * TRI) const946 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
947                                         const TargetRegisterInfo *TRI) const {
948   bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
949   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
950     const MachineOperand &MO = getOperand(i);
951     if (!MO.isReg() || !MO.isDef())
952       continue;
953     unsigned MOReg = MO.getReg();
954     bool Found = (MOReg == Reg);
955     if (!Found && TRI && isPhys &&
956         TargetRegisterInfo::isPhysicalRegister(MOReg)) {
957       if (Overlap)
958         Found = TRI->regsOverlap(MOReg, Reg);
959       else
960         Found = TRI->isSubRegister(MOReg, Reg);
961     }
962     if (Found && (!isDead || MO.isDead()))
963       return i;
964   }
965   return -1;
966 }
967 
968 /// findFirstPredOperandIdx() - Find the index of the first operand in the
969 /// operand list that is used to represent the predicate. It returns -1 if
970 /// none is found.
findFirstPredOperandIdx() const971 int MachineInstr::findFirstPredOperandIdx() const {
972   // Don't call MCID.findFirstPredOperandIdx() because this variant
973   // is sometimes called on an instruction that's not yet complete, and
974   // so the number of operands is less than the MCID indicates. In
975   // particular, the PTX target does this.
976   const MCInstrDesc &MCID = getDesc();
977   if (MCID.isPredicable()) {
978     for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
979       if (MCID.OpInfo[i].isPredicate())
980         return i;
981   }
982 
983   return -1;
984 }
985 
986 /// isRegTiedToUseOperand - Given the index of a register def operand,
987 /// check if the register def is tied to a source operand, due to either
988 /// two-address elimination or inline assembly constraints. Returns the
989 /// first tied use operand index by reference is UseOpIdx is not null.
990 bool MachineInstr::
isRegTiedToUseOperand(unsigned DefOpIdx,unsigned * UseOpIdx) const991 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
992   if (isInlineAsm()) {
993     assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
994     const MachineOperand &MO = getOperand(DefOpIdx);
995     if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
996       return false;
997     // Determine the actual operand index that corresponds to this index.
998     unsigned DefNo = 0;
999     int FlagIdx = findInlineAsmFlagIdx(DefOpIdx, &DefNo);
1000     if (FlagIdx < 0)
1001       return false;
1002 
1003     // Which part of the group is DefOpIdx?
1004     unsigned DefPart = DefOpIdx - (FlagIdx + 1);
1005 
1006     for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
1007          i != e; ++i) {
1008       const MachineOperand &FMO = getOperand(i);
1009       if (!FMO.isImm())
1010         continue;
1011       if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
1012         continue;
1013       unsigned Idx;
1014       if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
1015           Idx == DefNo) {
1016         if (UseOpIdx)
1017           *UseOpIdx = (unsigned)i + 1 + DefPart;
1018         return true;
1019       }
1020     }
1021     return false;
1022   }
1023 
1024   assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
1025   const MCInstrDesc &MCID = getDesc();
1026   for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
1027     const MachineOperand &MO = getOperand(i);
1028     if (MO.isReg() && MO.isUse() &&
1029         MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
1030       if (UseOpIdx)
1031         *UseOpIdx = (unsigned)i;
1032       return true;
1033     }
1034   }
1035   return false;
1036 }
1037 
1038 /// isRegTiedToDefOperand - Return true if the operand of the specified index
1039 /// is a register use and it is tied to an def operand. It also returns the def
1040 /// operand index by reference.
1041 bool MachineInstr::
isRegTiedToDefOperand(unsigned UseOpIdx,unsigned * DefOpIdx) const1042 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
1043   if (isInlineAsm()) {
1044     const MachineOperand &MO = getOperand(UseOpIdx);
1045     if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
1046       return false;
1047 
1048     // Find the flag operand corresponding to UseOpIdx
1049     int FlagIdx = findInlineAsmFlagIdx(UseOpIdx);
1050     if (FlagIdx < 0)
1051       return false;
1052 
1053     const MachineOperand &UFMO = getOperand(FlagIdx);
1054     unsigned DefNo;
1055     if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1056       if (!DefOpIdx)
1057         return true;
1058 
1059       unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1060       // Remember to adjust the index. First operand is asm string, second is
1061       // the HasSideEffects and AlignStack bits, then there is a flag for each.
1062       while (DefNo) {
1063         const MachineOperand &FMO = getOperand(DefIdx);
1064         assert(FMO.isImm());
1065         // Skip over this def.
1066         DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1067         --DefNo;
1068       }
1069       *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1070       return true;
1071     }
1072     return false;
1073   }
1074 
1075   const MCInstrDesc &MCID = getDesc();
1076   if (UseOpIdx >= MCID.getNumOperands())
1077     return false;
1078   const MachineOperand &MO = getOperand(UseOpIdx);
1079   if (!MO.isReg() || !MO.isUse())
1080     return false;
1081   int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
1082   if (DefIdx == -1)
1083     return false;
1084   if (DefOpIdx)
1085     *DefOpIdx = (unsigned)DefIdx;
1086   return true;
1087 }
1088 
1089 /// clearKillInfo - Clears kill flags on all operands.
1090 ///
clearKillInfo()1091 void MachineInstr::clearKillInfo() {
1092   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1093     MachineOperand &MO = getOperand(i);
1094     if (MO.isReg() && MO.isUse())
1095       MO.setIsKill(false);
1096   }
1097 }
1098 
1099 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1100 ///
copyKillDeadInfo(const MachineInstr * MI)1101 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1102   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1103     const MachineOperand &MO = MI->getOperand(i);
1104     if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1105       continue;
1106     for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1107       MachineOperand &MOp = getOperand(j);
1108       if (!MOp.isIdenticalTo(MO))
1109         continue;
1110       if (MO.isKill())
1111         MOp.setIsKill();
1112       else
1113         MOp.setIsDead();
1114       break;
1115     }
1116   }
1117 }
1118 
1119 /// copyPredicates - Copies predicate operand(s) from MI.
copyPredicates(const MachineInstr * MI)1120 void MachineInstr::copyPredicates(const MachineInstr *MI) {
1121   const MCInstrDesc &MCID = MI->getDesc();
1122   if (!MCID.isPredicable())
1123     return;
1124   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1125     if (MCID.OpInfo[i].isPredicate()) {
1126       // Predicated operands must be last operands.
1127       addOperand(MI->getOperand(i));
1128     }
1129   }
1130 }
1131 
substituteRegister(unsigned FromReg,unsigned ToReg,unsigned SubIdx,const TargetRegisterInfo & RegInfo)1132 void MachineInstr::substituteRegister(unsigned FromReg,
1133                                       unsigned ToReg,
1134                                       unsigned SubIdx,
1135                                       const TargetRegisterInfo &RegInfo) {
1136   if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1137     if (SubIdx)
1138       ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1139     for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1140       MachineOperand &MO = getOperand(i);
1141       if (!MO.isReg() || MO.getReg() != FromReg)
1142         continue;
1143       MO.substPhysReg(ToReg, RegInfo);
1144     }
1145   } else {
1146     for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1147       MachineOperand &MO = getOperand(i);
1148       if (!MO.isReg() || MO.getReg() != FromReg)
1149         continue;
1150       MO.substVirtReg(ToReg, SubIdx, RegInfo);
1151     }
1152   }
1153 }
1154 
1155 /// isSafeToMove - Return true if it is safe to move this instruction. If
1156 /// SawStore is set to true, it means that there is a store (or call) between
1157 /// the instruction's location and its intended destination.
isSafeToMove(const TargetInstrInfo * TII,AliasAnalysis * AA,bool & SawStore) const1158 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1159                                 AliasAnalysis *AA,
1160                                 bool &SawStore) const {
1161   // Ignore stuff that we obviously can't move.
1162   if (MCID->mayStore() || MCID->isCall()) {
1163     SawStore = true;
1164     return false;
1165   }
1166 
1167   if (isLabel() || isDebugValue() ||
1168       MCID->isTerminator() || hasUnmodeledSideEffects())
1169     return false;
1170 
1171   // See if this instruction does a load.  If so, we have to guarantee that the
1172   // loaded value doesn't change between the load and the its intended
1173   // destination. The check for isInvariantLoad gives the targe the chance to
1174   // classify the load as always returning a constant, e.g. a constant pool
1175   // load.
1176   if (MCID->mayLoad() && !isInvariantLoad(AA))
1177     // Otherwise, this is a real load.  If there is a store between the load and
1178     // end of block, or if the load is volatile, we can't move it.
1179     return !SawStore && !hasVolatileMemoryRef();
1180 
1181   return true;
1182 }
1183 
1184 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
1185 /// instruction which defined the specified register instead of copying it.
isSafeToReMat(const TargetInstrInfo * TII,AliasAnalysis * AA,unsigned DstReg) const1186 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1187                                  AliasAnalysis *AA,
1188                                  unsigned DstReg) const {
1189   bool SawStore = false;
1190   if (!TII->isTriviallyReMaterializable(this, AA) ||
1191       !isSafeToMove(TII, AA, SawStore))
1192     return false;
1193   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1194     const MachineOperand &MO = getOperand(i);
1195     if (!MO.isReg())
1196       continue;
1197     // FIXME: For now, do not remat any instruction with register operands.
1198     // Later on, we can loosen the restriction is the register operands have
1199     // not been modified between the def and use. Note, this is different from
1200     // MachineSink because the code is no longer in two-address form (at least
1201     // partially).
1202     if (MO.isUse())
1203       return false;
1204     else if (!MO.isDead() && MO.getReg() != DstReg)
1205       return false;
1206   }
1207   return true;
1208 }
1209 
1210 /// hasVolatileMemoryRef - Return true if this instruction may have a
1211 /// volatile memory reference, or if the information describing the
1212 /// memory reference is not available. Return false if it is known to
1213 /// have no volatile memory references.
hasVolatileMemoryRef() const1214 bool MachineInstr::hasVolatileMemoryRef() const {
1215   // An instruction known never to access memory won't have a volatile access.
1216   if (!MCID->mayStore() &&
1217       !MCID->mayLoad() &&
1218       !MCID->isCall() &&
1219       !hasUnmodeledSideEffects())
1220     return false;
1221 
1222   // Otherwise, if the instruction has no memory reference information,
1223   // conservatively assume it wasn't preserved.
1224   if (memoperands_empty())
1225     return true;
1226 
1227   // Check the memory reference information for volatile references.
1228   for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1229     if ((*I)->isVolatile())
1230       return true;
1231 
1232   return false;
1233 }
1234 
1235 /// isInvariantLoad - Return true if this instruction is loading from a
1236 /// location whose value is invariant across the function.  For example,
1237 /// loading a value from the constant pool or from the argument area
1238 /// of a function if it does not change.  This should only return true of
1239 /// *all* loads the instruction does are invariant (if it does multiple loads).
isInvariantLoad(AliasAnalysis * AA) const1240 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1241   // If the instruction doesn't load at all, it isn't an invariant load.
1242   if (!MCID->mayLoad())
1243     return false;
1244 
1245   // If the instruction has lost its memoperands, conservatively assume that
1246   // it may not be an invariant load.
1247   if (memoperands_empty())
1248     return false;
1249 
1250   const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1251 
1252   for (mmo_iterator I = memoperands_begin(),
1253        E = memoperands_end(); I != E; ++I) {
1254     if ((*I)->isVolatile()) return false;
1255     if ((*I)->isStore()) return false;
1256 
1257     if (const Value *V = (*I)->getValue()) {
1258       // A load from a constant PseudoSourceValue is invariant.
1259       if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1260         if (PSV->isConstant(MFI))
1261           continue;
1262       // If we have an AliasAnalysis, ask it whether the memory is constant.
1263       if (AA && AA->pointsToConstantMemory(
1264                       AliasAnalysis::Location(V, (*I)->getSize(),
1265                                               (*I)->getTBAAInfo())))
1266         continue;
1267     }
1268 
1269     // Otherwise assume conservatively.
1270     return false;
1271   }
1272 
1273   // Everything checks out.
1274   return true;
1275 }
1276 
1277 /// isConstantValuePHI - If the specified instruction is a PHI that always
1278 /// merges together the same virtual register, return the register, otherwise
1279 /// return 0.
isConstantValuePHI() const1280 unsigned MachineInstr::isConstantValuePHI() const {
1281   if (!isPHI())
1282     return 0;
1283   assert(getNumOperands() >= 3 &&
1284          "It's illegal to have a PHI without source operands");
1285 
1286   unsigned Reg = getOperand(1).getReg();
1287   for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1288     if (getOperand(i).getReg() != Reg)
1289       return 0;
1290   return Reg;
1291 }
1292 
hasUnmodeledSideEffects() const1293 bool MachineInstr::hasUnmodeledSideEffects() const {
1294   if (getDesc().hasUnmodeledSideEffects())
1295     return true;
1296   if (isInlineAsm()) {
1297     unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1298     if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1299       return true;
1300   }
1301 
1302   return false;
1303 }
1304 
1305 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1306 ///
allDefsAreDead() const1307 bool MachineInstr::allDefsAreDead() const {
1308   for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1309     const MachineOperand &MO = getOperand(i);
1310     if (!MO.isReg() || MO.isUse())
1311       continue;
1312     if (!MO.isDead())
1313       return false;
1314   }
1315   return true;
1316 }
1317 
1318 /// copyImplicitOps - Copy implicit register operands from specified
1319 /// instruction to this instruction.
copyImplicitOps(const MachineInstr * MI)1320 void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1321   for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1322        i != e; ++i) {
1323     const MachineOperand &MO = MI->getOperand(i);
1324     if (MO.isReg() && MO.isImplicit())
1325       addOperand(MO);
1326   }
1327 }
1328 
dump() const1329 void MachineInstr::dump() const {
1330   dbgs() << "  " << *this;
1331 }
1332 
printDebugLoc(DebugLoc DL,const MachineFunction * MF,raw_ostream & CommentOS)1333 static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1334                          raw_ostream &CommentOS) {
1335   const LLVMContext &Ctx = MF->getFunction()->getContext();
1336   if (!DL.isUnknown()) {          // Print source line info.
1337     DIScope Scope(DL.getScope(Ctx));
1338     // Omit the directory, because it's likely to be long and uninteresting.
1339     if (Scope.Verify())
1340       CommentOS << Scope.getFilename();
1341     else
1342       CommentOS << "<unknown>";
1343     CommentOS << ':' << DL.getLine();
1344     if (DL.getCol() != 0)
1345       CommentOS << ':' << DL.getCol();
1346     DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1347     if (!InlinedAtDL.isUnknown()) {
1348       CommentOS << " @[ ";
1349       printDebugLoc(InlinedAtDL, MF, CommentOS);
1350       CommentOS << " ]";
1351     }
1352   }
1353 }
1354 
print(raw_ostream & OS,const TargetMachine * TM) const1355 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1356   // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1357   const MachineFunction *MF = 0;
1358   const MachineRegisterInfo *MRI = 0;
1359   if (const MachineBasicBlock *MBB = getParent()) {
1360     MF = MBB->getParent();
1361     if (!TM && MF)
1362       TM = &MF->getTarget();
1363     if (MF)
1364       MRI = &MF->getRegInfo();
1365   }
1366 
1367   // Save a list of virtual registers.
1368   SmallVector<unsigned, 8> VirtRegs;
1369 
1370   // Print explicitly defined operands on the left of an assignment syntax.
1371   unsigned StartOp = 0, e = getNumOperands();
1372   for (; StartOp < e && getOperand(StartOp).isReg() &&
1373          getOperand(StartOp).isDef() &&
1374          !getOperand(StartOp).isImplicit();
1375        ++StartOp) {
1376     if (StartOp != 0) OS << ", ";
1377     getOperand(StartOp).print(OS, TM);
1378     unsigned Reg = getOperand(StartOp).getReg();
1379     if (TargetRegisterInfo::isVirtualRegister(Reg))
1380       VirtRegs.push_back(Reg);
1381   }
1382 
1383   if (StartOp != 0)
1384     OS << " = ";
1385 
1386   // Print the opcode name.
1387   OS << getDesc().getName();
1388 
1389   // Print the rest of the operands.
1390   bool OmittedAnyCallClobbers = false;
1391   bool FirstOp = true;
1392   unsigned AsmDescOp = ~0u;
1393   unsigned AsmOpCount = 0;
1394 
1395   if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1396     // Print asm string.
1397     OS << " ";
1398     getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1399 
1400     // Print HasSideEffects, IsAlignStack
1401     unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1402     if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1403       OS << " [sideeffect]";
1404     if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1405       OS << " [alignstack]";
1406 
1407     StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1408     FirstOp = false;
1409   }
1410 
1411 
1412   for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1413     const MachineOperand &MO = getOperand(i);
1414 
1415     if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1416       VirtRegs.push_back(MO.getReg());
1417 
1418     // Omit call-clobbered registers which aren't used anywhere. This makes
1419     // call instructions much less noisy on targets where calls clobber lots
1420     // of registers. Don't rely on MO.isDead() because we may be called before
1421     // LiveVariables is run, or we may be looking at a non-allocatable reg.
1422     if (MF && getDesc().isCall() &&
1423         MO.isReg() && MO.isImplicit() && MO.isDef()) {
1424       unsigned Reg = MO.getReg();
1425       if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1426         const MachineRegisterInfo &MRI = MF->getRegInfo();
1427         if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1428           bool HasAliasLive = false;
1429           for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1430                unsigned AliasReg = *Alias; ++Alias)
1431             if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1432               HasAliasLive = true;
1433               break;
1434             }
1435           if (!HasAliasLive) {
1436             OmittedAnyCallClobbers = true;
1437             continue;
1438           }
1439         }
1440       }
1441     }
1442 
1443     if (FirstOp) FirstOp = false; else OS << ",";
1444     OS << " ";
1445     if (i < getDesc().NumOperands) {
1446       const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1447       if (MCOI.isPredicate())
1448         OS << "pred:";
1449       if (MCOI.isOptionalDef())
1450         OS << "opt:";
1451     }
1452     if (isDebugValue() && MO.isMetadata()) {
1453       // Pretty print DBG_VALUE instructions.
1454       const MDNode *MD = MO.getMetadata();
1455       if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1456         OS << "!\"" << MDS->getString() << '\"';
1457       else
1458         MO.print(OS, TM);
1459     } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1460       OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1461     } else if (i == AsmDescOp && MO.isImm()) {
1462       // Pretty print the inline asm operand descriptor.
1463       OS << '$' << AsmOpCount++;
1464       unsigned Flag = MO.getImm();
1465       switch (InlineAsm::getKind(Flag)) {
1466       case InlineAsm::Kind_RegUse:             OS << ":[reguse"; break;
1467       case InlineAsm::Kind_RegDef:             OS << ":[regdef"; break;
1468       case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1469       case InlineAsm::Kind_Clobber:            OS << ":[clobber"; break;
1470       case InlineAsm::Kind_Imm:                OS << ":[imm"; break;
1471       case InlineAsm::Kind_Mem:                OS << ":[mem"; break;
1472       default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1473       }
1474 
1475       unsigned RCID = 0;
1476       if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1477         if (TM)
1478           OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1479         else
1480           OS << ":RC" << RCID;
1481       }
1482 
1483       unsigned TiedTo = 0;
1484       if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1485         OS << " tiedto:$" << TiedTo;
1486 
1487       OS << ']';
1488 
1489       // Compute the index of the next operand descriptor.
1490       AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1491     } else
1492       MO.print(OS, TM);
1493   }
1494 
1495   // Briefly indicate whether any call clobbers were omitted.
1496   if (OmittedAnyCallClobbers) {
1497     if (!FirstOp) OS << ",";
1498     OS << " ...";
1499   }
1500 
1501   bool HaveSemi = false;
1502   if (Flags) {
1503     if (!HaveSemi) OS << ";"; HaveSemi = true;
1504     OS << " flags: ";
1505 
1506     if (Flags & FrameSetup)
1507       OS << "FrameSetup";
1508   }
1509 
1510   if (!memoperands_empty()) {
1511     if (!HaveSemi) OS << ";"; HaveSemi = true;
1512 
1513     OS << " mem:";
1514     for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1515          i != e; ++i) {
1516       OS << **i;
1517       if (llvm::next(i) != e)
1518         OS << " ";
1519     }
1520   }
1521 
1522   // Print the regclass of any virtual registers encountered.
1523   if (MRI && !VirtRegs.empty()) {
1524     if (!HaveSemi) OS << ";"; HaveSemi = true;
1525     for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1526       const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1527       OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1528       for (unsigned j = i+1; j != VirtRegs.size();) {
1529         if (MRI->getRegClass(VirtRegs[j]) != RC) {
1530           ++j;
1531           continue;
1532         }
1533         if (VirtRegs[i] != VirtRegs[j])
1534           OS << "," << PrintReg(VirtRegs[j]);
1535         VirtRegs.erase(VirtRegs.begin()+j);
1536       }
1537     }
1538   }
1539 
1540   // Print debug location information.
1541   if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1542     if (!HaveSemi) OS << ";"; HaveSemi = true;
1543     DIVariable DV(getOperand(e - 1).getMetadata());
1544     OS << " line no:" <<  DV.getLineNumber();
1545     if (MDNode *InlinedAt = DV.getInlinedAt()) {
1546       DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1547       if (!InlinedAtDL.isUnknown()) {
1548         OS << " inlined @[ ";
1549         printDebugLoc(InlinedAtDL, MF, OS);
1550         OS << " ]";
1551       }
1552     }
1553   } else if (!debugLoc.isUnknown() && MF) {
1554     if (!HaveSemi) OS << ";"; HaveSemi = true;
1555     OS << " dbg:";
1556     printDebugLoc(debugLoc, MF, OS);
1557   }
1558 
1559   OS << '\n';
1560 }
1561 
addRegisterKilled(unsigned IncomingReg,const TargetRegisterInfo * RegInfo,bool AddIfNotFound)1562 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1563                                      const TargetRegisterInfo *RegInfo,
1564                                      bool AddIfNotFound) {
1565   bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1566   bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1567   bool Found = false;
1568   SmallVector<unsigned,4> DeadOps;
1569   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1570     MachineOperand &MO = getOperand(i);
1571     if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1572       continue;
1573     unsigned Reg = MO.getReg();
1574     if (!Reg)
1575       continue;
1576 
1577     if (Reg == IncomingReg) {
1578       if (!Found) {
1579         if (MO.isKill())
1580           // The register is already marked kill.
1581           return true;
1582         if (isPhysReg && isRegTiedToDefOperand(i))
1583           // Two-address uses of physregs must not be marked kill.
1584           return true;
1585         MO.setIsKill();
1586         Found = true;
1587       }
1588     } else if (hasAliases && MO.isKill() &&
1589                TargetRegisterInfo::isPhysicalRegister(Reg)) {
1590       // A super-register kill already exists.
1591       if (RegInfo->isSuperRegister(IncomingReg, Reg))
1592         return true;
1593       if (RegInfo->isSubRegister(IncomingReg, Reg))
1594         DeadOps.push_back(i);
1595     }
1596   }
1597 
1598   // Trim unneeded kill operands.
1599   while (!DeadOps.empty()) {
1600     unsigned OpIdx = DeadOps.back();
1601     if (getOperand(OpIdx).isImplicit())
1602       RemoveOperand(OpIdx);
1603     else
1604       getOperand(OpIdx).setIsKill(false);
1605     DeadOps.pop_back();
1606   }
1607 
1608   // If not found, this means an alias of one of the operands is killed. Add a
1609   // new implicit operand if required.
1610   if (!Found && AddIfNotFound) {
1611     addOperand(MachineOperand::CreateReg(IncomingReg,
1612                                          false /*IsDef*/,
1613                                          true  /*IsImp*/,
1614                                          true  /*IsKill*/));
1615     return true;
1616   }
1617   return Found;
1618 }
1619 
addRegisterDead(unsigned IncomingReg,const TargetRegisterInfo * RegInfo,bool AddIfNotFound)1620 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1621                                    const TargetRegisterInfo *RegInfo,
1622                                    bool AddIfNotFound) {
1623   bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1624   bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1625   bool Found = false;
1626   SmallVector<unsigned,4> DeadOps;
1627   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1628     MachineOperand &MO = getOperand(i);
1629     if (!MO.isReg() || !MO.isDef())
1630       continue;
1631     unsigned Reg = MO.getReg();
1632     if (!Reg)
1633       continue;
1634 
1635     if (Reg == IncomingReg) {
1636       MO.setIsDead();
1637       Found = true;
1638     } else if (hasAliases && MO.isDead() &&
1639                TargetRegisterInfo::isPhysicalRegister(Reg)) {
1640       // There exists a super-register that's marked dead.
1641       if (RegInfo->isSuperRegister(IncomingReg, Reg))
1642         return true;
1643       if (RegInfo->getSubRegisters(IncomingReg) &&
1644           RegInfo->getSuperRegisters(Reg) &&
1645           RegInfo->isSubRegister(IncomingReg, Reg))
1646         DeadOps.push_back(i);
1647     }
1648   }
1649 
1650   // Trim unneeded dead operands.
1651   while (!DeadOps.empty()) {
1652     unsigned OpIdx = DeadOps.back();
1653     if (getOperand(OpIdx).isImplicit())
1654       RemoveOperand(OpIdx);
1655     else
1656       getOperand(OpIdx).setIsDead(false);
1657     DeadOps.pop_back();
1658   }
1659 
1660   // If not found, this means an alias of one of the operands is dead. Add a
1661   // new implicit operand if required.
1662   if (Found || !AddIfNotFound)
1663     return Found;
1664 
1665   addOperand(MachineOperand::CreateReg(IncomingReg,
1666                                        true  /*IsDef*/,
1667                                        true  /*IsImp*/,
1668                                        false /*IsKill*/,
1669                                        true  /*IsDead*/));
1670   return true;
1671 }
1672 
addRegisterDefined(unsigned IncomingReg,const TargetRegisterInfo * RegInfo)1673 void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1674                                       const TargetRegisterInfo *RegInfo) {
1675   if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1676     MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1677     if (MO)
1678       return;
1679   } else {
1680     for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1681       const MachineOperand &MO = getOperand(i);
1682       if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1683           MO.getSubReg() == 0)
1684         return;
1685     }
1686   }
1687   addOperand(MachineOperand::CreateReg(IncomingReg,
1688                                        true  /*IsDef*/,
1689                                        true  /*IsImp*/));
1690 }
1691 
setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> & UsedRegs,const TargetRegisterInfo & TRI)1692 void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
1693                                          const TargetRegisterInfo &TRI) {
1694   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1695     MachineOperand &MO = getOperand(i);
1696     if (!MO.isReg() || !MO.isDef()) continue;
1697     unsigned Reg = MO.getReg();
1698     if (Reg == 0) continue;
1699     bool Dead = true;
1700     for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
1701          E = UsedRegs.end(); I != E; ++I)
1702       if (TRI.regsOverlap(*I, Reg)) {
1703         Dead = false;
1704         break;
1705       }
1706     // If there are no uses, including partial uses, the def is dead.
1707     if (Dead) MO.setIsDead();
1708   }
1709 }
1710 
1711 unsigned
getHashValue(const MachineInstr * const & MI)1712 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1713   unsigned Hash = MI->getOpcode() * 37;
1714   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1715     const MachineOperand &MO = MI->getOperand(i);
1716     uint64_t Key = (uint64_t)MO.getType() << 32;
1717     switch (MO.getType()) {
1718     default: break;
1719     case MachineOperand::MO_Register:
1720       if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1721         continue;  // Skip virtual register defs.
1722       Key |= MO.getReg();
1723       break;
1724     case MachineOperand::MO_Immediate:
1725       Key |= MO.getImm();
1726       break;
1727     case MachineOperand::MO_FrameIndex:
1728     case MachineOperand::MO_ConstantPoolIndex:
1729     case MachineOperand::MO_JumpTableIndex:
1730       Key |= MO.getIndex();
1731       break;
1732     case MachineOperand::MO_MachineBasicBlock:
1733       Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1734       break;
1735     case MachineOperand::MO_GlobalAddress:
1736       Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1737       break;
1738     case MachineOperand::MO_BlockAddress:
1739       Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1740       break;
1741     case MachineOperand::MO_MCSymbol:
1742       Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1743       break;
1744     }
1745     Key += ~(Key << 32);
1746     Key ^= (Key >> 22);
1747     Key += ~(Key << 13);
1748     Key ^= (Key >> 8);
1749     Key += (Key << 3);
1750     Key ^= (Key >> 15);
1751     Key += ~(Key << 27);
1752     Key ^= (Key >> 31);
1753     Hash = (unsigned)Key + Hash * 37;
1754   }
1755   return Hash;
1756 }
1757 
emitError(StringRef Msg) const1758 void MachineInstr::emitError(StringRef Msg) const {
1759   // Find the source location cookie.
1760   unsigned LocCookie = 0;
1761   const MDNode *LocMD = 0;
1762   for (unsigned i = getNumOperands(); i != 0; --i) {
1763     if (getOperand(i-1).isMetadata() &&
1764         (LocMD = getOperand(i-1).getMetadata()) &&
1765         LocMD->getNumOperands() != 0) {
1766       if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1767         LocCookie = CI->getZExtValue();
1768         break;
1769       }
1770     }
1771   }
1772 
1773   if (const MachineBasicBlock *MBB = getParent())
1774     if (const MachineFunction *MF = MBB->getParent())
1775       return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1776   report_fatal_error(Msg);
1777 }
1778