1 //===-- AlphaISelLowering.h - Alpha DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Alpha uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H 16 #define LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H 17 18 #include "llvm/ADT/VectorExtras.h" 19 #include "llvm/Target/TargetLowering.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "Alpha.h" 22 23 namespace llvm { 24 25 namespace AlphaISD { 26 enum NodeType { 27 // Start the numbering where the builting ops and target ops leave off. 28 FIRST_NUMBER = ISD::BUILTIN_OP_END, 29 //These corrospond to the identical Instruction 30 CVTQT_, CVTQS_, CVTTQ_, 31 32 /// GPRelHi/GPRelLo - These represent the high and low 16-bit 33 /// parts of a global address respectively. 34 GPRelHi, GPRelLo, 35 36 /// RetLit - Literal Relocation of a Global 37 RelLit, 38 39 /// GlobalRetAddr - used to restore the return address 40 GlobalRetAddr, 41 42 /// CALL - Normal call. 43 CALL, 44 45 /// DIVCALL - used for special library calls for div and rem 46 DivCall, 47 48 /// return flag operand 49 RET_FLAG, 50 51 /// CHAIN = COND_BRANCH CHAIN, OPC, (G|F)PRC, DESTBB [, INFLAG] - This 52 /// corresponds to the COND_BRANCH pseudo instruction. 53 /// *PRC is the input register to compare to zero, 54 /// OPC is the branch opcode to use (e.g. Alpha::BEQ), 55 /// DESTBB is the destination block to branch to, and INFLAG is 56 /// an optional input flag argument. 57 COND_BRANCH_I, COND_BRANCH_F 58 59 }; 60 } 61 62 class AlphaTargetLowering : public TargetLowering { 63 public: 64 explicit AlphaTargetLowering(TargetMachine &TM); 65 getShiftAmountTy(EVT LHSTy)66 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i64; } 67 68 /// getSetCCResultType - Get the SETCC result ValueType 69 virtual EVT getSetCCResultType(EVT VT) const; 70 71 /// LowerOperation - Provide custom lowering hooks for some operations. 72 /// 73 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 74 75 /// ReplaceNodeResults - Replace the results of node with an illegal result 76 /// type with new values built out of custom code. 77 /// 78 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 79 SelectionDAG &DAG) const; 80 81 // Friendly names for dumps 82 const char *getTargetNodeName(unsigned Opcode) const; 83 84 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 85 CallingConv::ID CallConv, bool isVarArg, 86 const SmallVectorImpl<ISD::InputArg> &Ins, 87 DebugLoc dl, SelectionDAG &DAG, 88 SmallVectorImpl<SDValue> &InVals) const; 89 90 ConstraintType getConstraintType(const std::string &Constraint) const; 91 92 /// Examine constraint string and operand type and determine a weight value. 93 /// The operand object must already have been set up with the operand type. 94 ConstraintWeight getSingleConstraintMatchWeight( 95 AsmOperandInfo &info, const char *constraint) const; 96 97 std::pair<unsigned, const TargetRegisterClass*> 98 getRegForInlineAsmConstraint(const std::string &Constraint, 99 EVT VT) const; 100 101 MachineBasicBlock * 102 EmitInstrWithCustomInserter(MachineInstr *MI, 103 MachineBasicBlock *BB) const; 104 105 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 106 107 /// isFPImmLegal - Returns true if the target can instruction select the 108 /// specified FP immediate natively. If false, the legalizer will 109 /// materialize the FP immediate as a load from a constant pool. 110 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 111 112 private: 113 // Helpers for custom lowering. 114 void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr, 115 SelectionDAG &DAG) const; 116 117 virtual SDValue 118 LowerFormalArguments(SDValue Chain, 119 CallingConv::ID CallConv, bool isVarArg, 120 const SmallVectorImpl<ISD::InputArg> &Ins, 121 DebugLoc dl, SelectionDAG &DAG, 122 SmallVectorImpl<SDValue> &InVals) const; 123 124 virtual SDValue 125 LowerCall(SDValue Chain, SDValue Callee, 126 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 127 const SmallVectorImpl<ISD::OutputArg> &Outs, 128 const SmallVectorImpl<SDValue> &OutVals, 129 const SmallVectorImpl<ISD::InputArg> &Ins, 130 DebugLoc dl, SelectionDAG &DAG, 131 SmallVectorImpl<SDValue> &InVals) const; 132 133 virtual SDValue 134 LowerReturn(SDValue Chain, 135 CallingConv::ID CallConv, bool isVarArg, 136 const SmallVectorImpl<ISD::OutputArg> &Outs, 137 const SmallVectorImpl<SDValue> &OutVals, 138 DebugLoc dl, SelectionDAG &DAG) const; 139 }; 140 } 141 142 #endif // LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H 143