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MCTargetDesc/03-May-2024-222100

TargetInfo/03-May-2024-3713

CellSDKIntrinsics.tdD03-May-202419 KiB450377

MakefileD03-May-2024642 219

README.txtD03-May-20243.2 KiB9369

SPU.hD03-May-2024937 3212

SPU.tdD03-May-20242.1 KiB6751

SPU128InstrInfo.tdD03-May-20241.5 KiB4232

SPU64InstrInfo.tdD03-May-202415.8 KiB409324

SPUAsmPrinter.cppD03-May-202411.1 KiB335264

SPUCallingConv.tdD03-May-20242.8 KiB5851

SPUFrameLowering.cppD03-May-20249.7 KiB256167

SPUFrameLowering.hD03-May-20242.5 KiB8138

SPUHazardRecognizers.cppD03-May-20243.5 KiB142102

SPUHazardRecognizers.hD03-May-20241 KiB4219

SPUISelDAGToDAG.cppD03-May-202443.4 KiB1,204897

SPUISelLowering.cppD03-May-2024119.1 KiB3,2642,321

SPUISelLowering.hD03-May-20247.7 KiB187120

SPUInstrBuilder.hD03-May-20241.4 KiB4414

SPUInstrFormats.tdD03-May-20249.6 KiB321269

SPUInstrInfo.cppD03-May-202414.2 KiB454349

SPUInstrInfo.hD03-May-20243.4 KiB8549

SPUInstrInfo.tdD03-May-2024157.8 KiB4,4853,550

SPUMachineFunction.hD03-May-20241.3 KiB5020

SPUMathInstr.tdD03-May-20244.4 KiB9885

SPUNodes.tdD03-May-20246.3 KiB160124

SPUNopFiller.cppD03-May-20244.7 KiB154106

SPUOperands.tdD03-May-202420.8 KiB665540

SPURegisterInfo.cppD03-May-202411.3 KiB357291

SPURegisterInfo.hD03-May-20243.6 KiB10241

SPURegisterInfo.tdD03-May-20248.5 KiB184170

SPURegisterNames.hD03-May-2024582 205

SPUSchedule.tdD03-May-20243.1 KiB6054

SPUSelectionDAGInfo.cppD03-May-2024737 248

SPUSelectionDAGInfo.hD03-May-2024828 3212

SPUSubtarget.cppD03-May-20242.3 KiB6736

SPUSubtarget.hD03-May-20243.2 KiB9845

SPUTargetMachine.cppD03-May-20242.5 KiB7544

SPUTargetMachine.hD03-May-20242.5 KiB9258

README.txt

1//===- README.txt - Notes for improving CellSPU-specific code gen ---------===//
2
3This code was contributed by a team from the Computer Systems Research
4Department in The Aerospace Corporation:
5
6- Scott Michel (head bottle washer and much of the non-floating point
7  instructions)
8- Mark Thomas (floating point instructions)
9- Michael AuYeung (intrinsics)
10- Chandler Carruth (LLVM expertise)
11- Nehal Desai (debugging, i32 operations, RoadRunner SPU expertise)
12
13Some minor fixes added by Kalle Raiskila.
14
15THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR
18OTHERWISE.  IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES
19OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING
20OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT
21LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR
22REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL,
23OR PUNITIVE  DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR
24SUCH DAMAGES ARE FORESEEABLE.
25
26---------------------------------------------------------------------------
27--WARNING--:
28--WARNING--: The CellSPU work is work-in-progress and "alpha" quality code.
29--WARNING--:
30
31If you are brave enough to try this code or help to hack on it, be sure
32to add 'spu' to configure's --enable-targets option, e.g.:
33
34        ./configure <your_configure_flags_here> \
35           --enable-targets=x86,x86_64,powerpc,spu
36
37---------------------------------------------------------------------------
38
39TODO:
40* Create a machine pass for performing dual-pipeline scheduling specifically
41  for CellSPU, and insert branch prediction instructions as needed.
42
43* i32 instructions:
44
45  * i32 division (work-in-progress)
46
47* i64 support (see i64operations.c test harness):
48
49  * shifts and comparison operators: done
50  * sign and zero extension: done
51  * addition: done
52  * subtraction: needed
53  * multiplication: done
54
55* i128 support:
56
57  * zero extension, any extension: done
58  * sign extension: done
59  * arithmetic operators (add, sub, mul, div): needed
60  * logical operations (and, or, shl, srl, sra, xor, nor, nand): needed
61
62    * or: done
63
64* f64 support
65
66  * Comparison operators:
67    SETOEQ              unimplemented
68    SETOGT              unimplemented
69    SETOGE              unimplemented
70    SETOLT              unimplemented
71    SETOLE              unimplemented
72    SETONE              unimplemented
73    SETO                done (lowered)
74    SETUO               done (lowered)
75    SETUEQ              unimplemented
76    SETUGT              unimplemented
77    SETUGE              unimplemented
78    SETULT              unimplemented
79    SETULE              unimplemented
80    SETUNE              unimplemented
81
82* LLVM vector suport
83
84  * VSETCC needs to be implemented. It's pretty straightforward to code, but
85    needs implementation.
86
87* Intrinsics
88
89  * spu.h instrinsics added but not tested. Need to have an operational
90    llvm-spu-gcc in order to write a unit test harness.
91
92===-------------------------------------------------------------------------===
93