1//=- HexagonIntrinsicsV60.td - Target Description for Hexagon -*- tablegen *-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Hexagon V60 Compiler Intrinsics in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14 15let AddedComplexity = 100 in { 16def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))), 17 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >; 18 19def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))), 20 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >; 21 22def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))), 23 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >; 24 25def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))), 26 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >; 27} 28 29def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))), 30 (v512i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; 31 32def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))), 33 (v512i1 (V6_vandvrt(v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; 34 35def : Pat <(v512i1 (bitconvert (v64i8 HvxVR:$src1))), 36 (v512i1 (V6_vandvrt(v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; 37 38def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))), 39 (v16i32 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; 40 41def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))), 42 (v32i16 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; 43 44def : Pat <(v64i8 (bitconvert (v512i1 HvxQR:$src1))), 45 (v64i8 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; 46 47def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))), 48 (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; 49 50def : Pat <(v1024i1 (bitconvert (v64i16 HvxVR:$src1))), 51 (v1024i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; 52 53def : Pat <(v1024i1 (bitconvert (v128i8 HvxVR:$src1))), 54 (v1024i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>; 55 56def : Pat <(v32i32 (bitconvert (v1024i1 HvxQR:$src1))), 57 (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; 58 59def : Pat <(v64i16 (bitconvert (v1024i1 HvxQR:$src1))), 60 (v64i16 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; 61 62def : Pat <(v128i8 (bitconvert (v1024i1 HvxQR:$src1))), 63 (v128i8 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>; 64 65let AddedComplexity = 140 in { 66def : Pat <(store (v512i1 HvxQR:$src1), (i32 IntRegs:$addr)), 67 (V6_vS32b_ai IntRegs:$addr, 0, 68 (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1), 69 (A2_tfrsi 0x01010101))))>; 70 71def : Pat <(v512i1 (load (i32 IntRegs:$addr))), 72 (v512i1 (V6_vandvrt 73 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>; 74 75def : Pat <(store (v1024i1 HvxQR:$src1), (i32 IntRegs:$addr)), 76 (V6_vS32b_ai IntRegs:$addr, 0, 77 (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), 78 (A2_tfrsi 0x01010101))))>; 79 80def : Pat <(v1024i1 (load (i32 IntRegs:$addr))), 81 (v1024i1 (V6_vandvrt 82 (v32i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>; 83} 84 85multiclass T_R_pat <InstHexagon MI, Intrinsic IntID> { 86 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>; 87 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1), 88 (MI IntRegs:$src1)>; 89} 90 91multiclass T_V_pat <InstHexagon MI, Intrinsic IntID> { 92 def: Pat<(IntID HvxVR:$src1), 93 (MI HvxVR:$src1)>; 94 95 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1), 96 (MI HvxVR:$src1)>; 97} 98 99multiclass T_W_pat <InstHexagon MI, Intrinsic IntID> { 100 def: Pat<(IntID HvxWR:$src1), 101 (MI HvxWR:$src1)>; 102 103 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1), 104 (MI HvxWR:$src1)>; 105} 106 107multiclass T_Q_pat <InstHexagon MI, Intrinsic IntID> { 108 def: Pat<(IntID HvxQR:$src1), 109 (MI HvxQR:$src1)>; 110 111 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1), 112 (MI HvxQR:$src1)>; 113} 114 115multiclass T_WR_pat <InstHexagon MI, Intrinsic IntID> { 116 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2), 117 (MI HvxWR:$src1, IntRegs:$src2)>; 118 119 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxWR:$src1, IntRegs:$src2), 120 (MI HvxWR:$src1, IntRegs:$src2)>; 121} 122 123multiclass T_VR_pat <InstHexagon MI, Intrinsic IntID> { 124 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2), 125 (MI HvxVR:$src1, IntRegs:$src2)>; 126 127 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxVR:$src1, IntRegs:$src2), 128 (MI HvxVR:$src1, IntRegs:$src2)>; 129} 130 131multiclass T_WV_pat <InstHexagon MI, Intrinsic IntID> { 132 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2), 133 (MI HvxWR:$src1, HvxVR:$src2)>; 134 135 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2), 136 (MI HvxWR:$src1, HvxVR:$src2)>; 137} 138 139multiclass T_WW_pat <InstHexagon MI, Intrinsic IntID> { 140 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2), 141 (MI HvxWR:$src1, HvxWR:$src2)>; 142 143 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2), 144 (MI HvxWR:$src1, HvxWR:$src2)>; 145} 146 147multiclass T_VV_pat <InstHexagon MI, Intrinsic IntID> { 148 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2), 149 (MI HvxVR:$src1, HvxVR:$src2)>; 150 151 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2), 152 (MI HvxVR:$src1, HvxVR:$src2)>; 153} 154 155multiclass T_QR_pat <InstHexagon MI, Intrinsic IntID> { 156 def: Pat<(IntID HvxQR:$src1, IntRegs:$src2), 157 (MI HvxQR:$src1, IntRegs:$src2)>; 158 159 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2), 160 (MI HvxQR:$src1, IntRegs:$src2)>; 161} 162 163multiclass T_QQ_pat <InstHexagon MI, Intrinsic IntID> { 164 def: Pat<(IntID HvxQR:$src1, HvxQR:$src2), 165 (MI HvxQR:$src1, HvxQR:$src2)>; 166 167 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxQR:$src2), 168 (MI HvxQR:$src1, HvxQR:$src2)>; 169} 170 171multiclass T_WWR_pat <InstHexagon MI, Intrinsic IntID> { 172 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), 173 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>; 174 175 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2, 176 IntRegs:$src3), 177 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>; 178} 179 180multiclass T_VVR_pat <InstHexagon MI, Intrinsic IntID> { 181 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), 182 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>; 183 184 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, 185 IntRegs:$src3), 186 (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>; 187} 188 189multiclass T_WVR_pat <InstHexagon MI, Intrinsic IntID> { 190 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), 191 (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>; 192 193 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2, 194 IntRegs:$src3), 195 (MI HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>; 196} 197 198multiclass T_VWR_pat <InstHexagon MI, Intrinsic IntID> { 199 def: Pat<(IntID HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), 200 (MI HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>; 201 202 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxWR:$src2, 203 IntRegs:$src3), 204 (MI HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>; 205} 206 207multiclass T_VVV_pat <InstHexagon MI, Intrinsic IntID> { 208 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), 209 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>; 210 211 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, 212 HvxVR:$src3), 213 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>; 214} 215 216multiclass T_WVV_pat <InstHexagon MI, Intrinsic IntID> { 217 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), 218 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>; 219 220 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2, 221 HvxVR:$src3), 222 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>; 223} 224 225multiclass T_QVV_pat <InstHexagon MI, Intrinsic IntID> { 226 def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), 227 (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>; 228 229 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2, 230 HvxVR:$src3), 231 (MI HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>; 232} 233 234multiclass T_VQR_pat <InstHexagon MI, Intrinsic IntID> { 235 def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), 236 (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>; 237 238 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxQR:$src2, 239 IntRegs:$src3), 240 (MI HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>; 241} 242 243 244multiclass T_QVR_pat <InstHexagon MI, Intrinsic IntID> { 245 def: Pat<(IntID HvxQR:$src1, HvxVR:$src2, IntRegs:$src3), 246 (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>; 247 248 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2, 249 IntRegs:$src3), 250 (MI HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>; 251} 252 253multiclass T_VVI_pat <InstHexagon MI, Intrinsic IntID> { 254 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3), 255 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>; 256 257 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, 258 HvxVR:$src2, imm:$src3), 259 (MI HvxVR:$src1, HvxVR:$src2, imm:$src3)>; 260} 261 262multiclass T_WRI_pat <InstHexagon MI, Intrinsic IntID> { 263 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2, imm:$src3), 264 (MI HvxWR:$src1, IntRegs:$src2, imm:$src3)>; 265 266 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, 267 IntRegs:$src2, imm:$src3), 268 (MI HvxWR:$src1, IntRegs:$src2, imm:$src3)>; 269} 270 271multiclass T_WWRI_pat <InstHexagon MI, Intrinsic IntID> { 272 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4), 273 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>; 274 275 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2, 276 IntRegs:$src3, imm:$src4), 277 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, imm:$src4)>; 278} 279 280multiclass T_VVVR_pat <InstHexagon MI, Intrinsic IntID> { 281 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4), 282 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; 283 284 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, 285 HvxVR:$src3, IntRegs:$src4), 286 (MI HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; 287} 288 289multiclass T_WVVR_pat <InstHexagon MI, Intrinsic IntID> { 290 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4), 291 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; 292 293 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2, 294 HvxVR:$src3, IntRegs:$src4), 295 (MI HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegs:$src4)>; 296} 297 298defm : T_WR_pat <V6_vtmpyb, int_hexagon_V6_vtmpyb>; 299defm : T_WR_pat <V6_vtmpybus, int_hexagon_V6_vtmpybus>; 300defm : T_VR_pat <V6_vdmpyhb, int_hexagon_V6_vdmpyhb>; 301defm : T_VR_pat <V6_vrmpyub, int_hexagon_V6_vrmpyub>; 302defm : T_VR_pat <V6_vrmpybus, int_hexagon_V6_vrmpybus>; 303defm : T_WR_pat <V6_vdsaduh, int_hexagon_V6_vdsaduh>; 304defm : T_VR_pat <V6_vdmpybus, int_hexagon_V6_vdmpybus>; 305defm : T_WR_pat <V6_vdmpybus_dv, int_hexagon_V6_vdmpybus_dv>; 306defm : T_VR_pat <V6_vdmpyhsusat, int_hexagon_V6_vdmpyhsusat>; 307defm : T_WR_pat <V6_vdmpyhsuisat, int_hexagon_V6_vdmpyhsuisat>; 308defm : T_VR_pat <V6_vdmpyhsat, int_hexagon_V6_vdmpyhsat>; 309defm : T_WR_pat <V6_vdmpyhisat, int_hexagon_V6_vdmpyhisat>; 310defm : T_WR_pat <V6_vdmpyhb_dv, int_hexagon_V6_vdmpyhb_dv>; 311defm : T_VR_pat <V6_vmpybus, int_hexagon_V6_vmpybus>; 312defm : T_WR_pat <V6_vmpabus, int_hexagon_V6_vmpabus>; 313defm : T_WR_pat <V6_vmpahb, int_hexagon_V6_vmpahb>; 314defm : T_VR_pat <V6_vmpyh, int_hexagon_V6_vmpyh>; 315defm : T_VR_pat <V6_vmpyhss, int_hexagon_V6_vmpyhss>; 316defm : T_VR_pat <V6_vmpyhsrs, int_hexagon_V6_vmpyhsrs>; 317defm : T_VR_pat <V6_vmpyuh, int_hexagon_V6_vmpyuh>; 318defm : T_VR_pat <V6_vmpyihb, int_hexagon_V6_vmpyihb>; 319defm : T_VR_pat <V6_vror, int_hexagon_V6_vror>; 320defm : T_VR_pat <V6_vasrw, int_hexagon_V6_vasrw>; 321defm : T_VR_pat <V6_vasrh, int_hexagon_V6_vasrh>; 322defm : T_VR_pat <V6_vaslw, int_hexagon_V6_vaslw>; 323defm : T_VR_pat <V6_vaslh, int_hexagon_V6_vaslh>; 324defm : T_VR_pat <V6_vlsrw, int_hexagon_V6_vlsrw>; 325defm : T_VR_pat <V6_vlsrh, int_hexagon_V6_vlsrh>; 326defm : T_VR_pat <V6_vmpyiwh, int_hexagon_V6_vmpyiwh>; 327defm : T_VR_pat <V6_vmpyiwb, int_hexagon_V6_vmpyiwb>; 328defm : T_WR_pat <V6_vtmpyhb, int_hexagon_V6_vtmpyhb>; 329defm : T_VR_pat <V6_vmpyub, int_hexagon_V6_vmpyub>; 330 331defm : T_VV_pat <V6_vrmpyubv, int_hexagon_V6_vrmpyubv>; 332defm : T_VV_pat <V6_vrmpybv, int_hexagon_V6_vrmpybv>; 333defm : T_VV_pat <V6_vrmpybusv, int_hexagon_V6_vrmpybusv>; 334defm : T_VV_pat <V6_vdmpyhvsat, int_hexagon_V6_vdmpyhvsat>; 335defm : T_VV_pat <V6_vmpybv, int_hexagon_V6_vmpybv>; 336defm : T_VV_pat <V6_vmpyubv, int_hexagon_V6_vmpyubv>; 337defm : T_VV_pat <V6_vmpybusv, int_hexagon_V6_vmpybusv>; 338defm : T_VV_pat <V6_vmpyhv, int_hexagon_V6_vmpyhv>; 339defm : T_VV_pat <V6_vmpyuhv, int_hexagon_V6_vmpyuhv>; 340defm : T_VV_pat <V6_vmpyhvsrs, int_hexagon_V6_vmpyhvsrs>; 341defm : T_VV_pat <V6_vmpyhus, int_hexagon_V6_vmpyhus>; 342defm : T_WW_pat <V6_vmpabusv, int_hexagon_V6_vmpabusv>; 343defm : T_VV_pat <V6_vmpyih, int_hexagon_V6_vmpyih>; 344defm : T_VV_pat <V6_vand, int_hexagon_V6_vand>; 345defm : T_VV_pat <V6_vor, int_hexagon_V6_vor>; 346defm : T_VV_pat <V6_vxor, int_hexagon_V6_vxor>; 347defm : T_VV_pat <V6_vaddw, int_hexagon_V6_vaddw>; 348defm : T_VV_pat <V6_vaddubsat, int_hexagon_V6_vaddubsat>; 349defm : T_VV_pat <V6_vadduhsat, int_hexagon_V6_vadduhsat>; 350defm : T_VV_pat <V6_vaddhsat, int_hexagon_V6_vaddhsat>; 351defm : T_VV_pat <V6_vaddwsat, int_hexagon_V6_vaddwsat>; 352defm : T_VV_pat <V6_vsubb, int_hexagon_V6_vsubb>; 353defm : T_VV_pat <V6_vsubh, int_hexagon_V6_vsubh>; 354defm : T_VV_pat <V6_vsubw, int_hexagon_V6_vsubw>; 355defm : T_VV_pat <V6_vsububsat, int_hexagon_V6_vsububsat>; 356defm : T_VV_pat <V6_vsubuhsat, int_hexagon_V6_vsubuhsat>; 357defm : T_VV_pat <V6_vsubhsat, int_hexagon_V6_vsubhsat>; 358defm : T_VV_pat <V6_vsubwsat, int_hexagon_V6_vsubwsat>; 359defm : T_WW_pat <V6_vaddb_dv, int_hexagon_V6_vaddb_dv>; 360defm : T_WW_pat <V6_vaddh_dv, int_hexagon_V6_vaddh_dv>; 361defm : T_WW_pat <V6_vaddw_dv, int_hexagon_V6_vaddw_dv>; 362defm : T_WW_pat <V6_vaddubsat_dv, int_hexagon_V6_vaddubsat_dv>; 363defm : T_WW_pat <V6_vadduhsat_dv, int_hexagon_V6_vadduhsat_dv>; 364defm : T_WW_pat <V6_vaddhsat_dv, int_hexagon_V6_vaddhsat_dv>; 365defm : T_WW_pat <V6_vaddwsat_dv, int_hexagon_V6_vaddwsat_dv>; 366defm : T_WW_pat <V6_vsubb_dv, int_hexagon_V6_vsubb_dv>; 367defm : T_WW_pat <V6_vsubh_dv, int_hexagon_V6_vsubh_dv>; 368defm : T_WW_pat <V6_vsubw_dv, int_hexagon_V6_vsubw_dv>; 369defm : T_WW_pat <V6_vsububsat_dv, int_hexagon_V6_vsububsat_dv>; 370defm : T_WW_pat <V6_vsubuhsat_dv, int_hexagon_V6_vsubuhsat_dv>; 371defm : T_WW_pat <V6_vsubhsat_dv, int_hexagon_V6_vsubhsat_dv>; 372defm : T_WW_pat <V6_vsubwsat_dv, int_hexagon_V6_vsubwsat_dv>; 373defm : T_VV_pat <V6_vaddubh, int_hexagon_V6_vaddubh>; 374defm : T_VV_pat <V6_vadduhw, int_hexagon_V6_vadduhw>; 375defm : T_VV_pat <V6_vaddhw, int_hexagon_V6_vaddhw>; 376defm : T_VV_pat <V6_vsububh, int_hexagon_V6_vsububh>; 377defm : T_VV_pat <V6_vsubuhw, int_hexagon_V6_vsubuhw>; 378defm : T_VV_pat <V6_vsubhw, int_hexagon_V6_vsubhw>; 379defm : T_VV_pat <V6_vabsdiffub, int_hexagon_V6_vabsdiffub>; 380defm : T_VV_pat <V6_vabsdiffh, int_hexagon_V6_vabsdiffh>; 381defm : T_VV_pat <V6_vabsdiffuh, int_hexagon_V6_vabsdiffuh>; 382defm : T_VV_pat <V6_vabsdiffw, int_hexagon_V6_vabsdiffw>; 383defm : T_VV_pat <V6_vavgub, int_hexagon_V6_vavgub>; 384defm : T_VV_pat <V6_vavguh, int_hexagon_V6_vavguh>; 385defm : T_VV_pat <V6_vavgh, int_hexagon_V6_vavgh>; 386defm : T_VV_pat <V6_vavgw, int_hexagon_V6_vavgw>; 387defm : T_VV_pat <V6_vnavgub, int_hexagon_V6_vnavgub>; 388defm : T_VV_pat <V6_vnavgh, int_hexagon_V6_vnavgh>; 389defm : T_VV_pat <V6_vnavgw, int_hexagon_V6_vnavgw>; 390defm : T_VV_pat <V6_vavgubrnd, int_hexagon_V6_vavgubrnd>; 391defm : T_VV_pat <V6_vavguhrnd, int_hexagon_V6_vavguhrnd>; 392defm : T_VV_pat <V6_vavghrnd, int_hexagon_V6_vavghrnd>; 393defm : T_VV_pat <V6_vavgwrnd, int_hexagon_V6_vavgwrnd>; 394defm : T_WW_pat <V6_vmpabuuv, int_hexagon_V6_vmpabuuv>; 395 396defm : T_VVR_pat <V6_vdmpyhb_acc, int_hexagon_V6_vdmpyhb_acc>; 397defm : T_VVR_pat <V6_vrmpyub_acc, int_hexagon_V6_vrmpyub_acc>; 398defm : T_VVR_pat <V6_vrmpybus_acc, int_hexagon_V6_vrmpybus_acc>; 399defm : T_VVR_pat <V6_vdmpybus_acc, int_hexagon_V6_vdmpybus_acc>; 400defm : T_VVR_pat <V6_vdmpyhsusat_acc, int_hexagon_V6_vdmpyhsusat_acc>; 401defm : T_VVR_pat <V6_vdmpyhsat_acc, int_hexagon_V6_vdmpyhsat_acc>; 402defm : T_VVR_pat <V6_vmpyiwb_acc, int_hexagon_V6_vmpyiwb_acc>; 403defm : T_VVR_pat <V6_vmpyiwh_acc, int_hexagon_V6_vmpyiwh_acc>; 404defm : T_VVR_pat <V6_vmpyihb_acc, int_hexagon_V6_vmpyihb_acc>; 405defm : T_VVR_pat <V6_vaslw_acc, int_hexagon_V6_vaslw_acc>; 406defm : T_VVR_pat <V6_vasrw_acc, int_hexagon_V6_vasrw_acc>; 407 408defm : T_VWR_pat <V6_vdmpyhsuisat_acc, int_hexagon_V6_vdmpyhsuisat_acc>; 409defm : T_VWR_pat <V6_vdmpyhisat_acc, int_hexagon_V6_vdmpyhisat_acc>; 410 411defm : T_WVR_pat <V6_vmpybus_acc, int_hexagon_V6_vmpybus_acc>; 412defm : T_WVR_pat <V6_vmpyhsat_acc, int_hexagon_V6_vmpyhsat_acc>; 413defm : T_WVR_pat <V6_vmpyuh_acc, int_hexagon_V6_vmpyuh_acc>; 414defm : T_WVR_pat <V6_vmpyub_acc, int_hexagon_V6_vmpyub_acc>; 415 416defm : T_WWR_pat <V6_vtmpyb_acc, int_hexagon_V6_vtmpyb_acc>; 417defm : T_WWR_pat <V6_vtmpybus_acc, int_hexagon_V6_vtmpybus_acc>; 418defm : T_WWR_pat <V6_vtmpyhb_acc, int_hexagon_V6_vtmpyhb_acc>; 419defm : T_WWR_pat <V6_vdmpybus_dv_acc, int_hexagon_V6_vdmpybus_dv_acc>; 420defm : T_WWR_pat <V6_vdmpyhb_dv_acc, int_hexagon_V6_vdmpyhb_dv_acc>; 421defm : T_WWR_pat <V6_vmpabus_acc, int_hexagon_V6_vmpabus_acc>; 422defm : T_WWR_pat <V6_vmpahb_acc, int_hexagon_V6_vmpahb_acc>; 423defm : T_WWR_pat <V6_vdsaduh_acc, int_hexagon_V6_vdsaduh_acc>; 424 425defm : T_VVV_pat <V6_vdmpyhvsat_acc, int_hexagon_V6_vdmpyhvsat_acc>; 426defm : T_WVV_pat <V6_vmpybusv_acc, int_hexagon_V6_vmpybusv_acc>; 427defm : T_WVV_pat <V6_vmpybv_acc, int_hexagon_V6_vmpybv_acc>; 428defm : T_WVV_pat <V6_vmpyhus_acc, int_hexagon_V6_vmpyhus_acc>; 429defm : T_WVV_pat <V6_vmpyhv_acc, int_hexagon_V6_vmpyhv_acc>; 430defm : T_VVV_pat <V6_vmpyiewh_acc, int_hexagon_V6_vmpyiewh_acc>; 431defm : T_VVV_pat <V6_vmpyiewuh_acc, int_hexagon_V6_vmpyiewuh_acc>; 432defm : T_VVV_pat <V6_vmpyih_acc, int_hexagon_V6_vmpyih_acc>; 433defm : T_VVV_pat <V6_vmpyowh_rnd_sacc, int_hexagon_V6_vmpyowh_rnd_sacc>; 434defm : T_VVV_pat <V6_vmpyowh_sacc, int_hexagon_V6_vmpyowh_sacc>; 435defm : T_WVV_pat <V6_vmpyubv_acc, int_hexagon_V6_vmpyubv_acc>; 436defm : T_WVV_pat <V6_vmpyuhv_acc, int_hexagon_V6_vmpyuhv_acc>; 437defm : T_VVV_pat <V6_vrmpybusv_acc, int_hexagon_V6_vrmpybusv_acc>; 438defm : T_VVV_pat <V6_vrmpybv_acc, int_hexagon_V6_vrmpybv_acc>; 439defm : T_VVV_pat <V6_vrmpyubv_acc, int_hexagon_V6_vrmpyubv_acc>; 440 441// Compare instructions 442defm : T_QVV_pat <V6_veqb_and, int_hexagon_V6_veqb_and>; 443defm : T_QVV_pat <V6_veqh_and, int_hexagon_V6_veqh_and>; 444defm : T_QVV_pat <V6_veqw_and, int_hexagon_V6_veqw_and>; 445defm : T_QVV_pat <V6_vgtb_and, int_hexagon_V6_vgtb_and>; 446defm : T_QVV_pat <V6_vgth_and, int_hexagon_V6_vgth_and>; 447defm : T_QVV_pat <V6_vgtw_and, int_hexagon_V6_vgtw_and>; 448defm : T_QVV_pat <V6_vgtub_and, int_hexagon_V6_vgtub_and>; 449defm : T_QVV_pat <V6_vgtuh_and, int_hexagon_V6_vgtuh_and>; 450defm : T_QVV_pat <V6_vgtuw_and, int_hexagon_V6_vgtuw_and>; 451defm : T_QVV_pat <V6_veqb_or, int_hexagon_V6_veqb_or>; 452defm : T_QVV_pat <V6_veqh_or, int_hexagon_V6_veqh_or>; 453defm : T_QVV_pat <V6_veqw_or, int_hexagon_V6_veqw_or>; 454defm : T_QVV_pat <V6_vgtb_or, int_hexagon_V6_vgtb_or>; 455defm : T_QVV_pat <V6_vgth_or, int_hexagon_V6_vgth_or>; 456defm : T_QVV_pat <V6_vgtw_or, int_hexagon_V6_vgtw_or>; 457defm : T_QVV_pat <V6_vgtub_or, int_hexagon_V6_vgtub_or>; 458defm : T_QVV_pat <V6_vgtuh_or, int_hexagon_V6_vgtuh_or>; 459defm : T_QVV_pat <V6_vgtuw_or, int_hexagon_V6_vgtuw_or>; 460defm : T_QVV_pat <V6_veqb_xor, int_hexagon_V6_veqb_xor>; 461defm : T_QVV_pat <V6_veqh_xor, int_hexagon_V6_veqh_xor>; 462defm : T_QVV_pat <V6_veqw_xor, int_hexagon_V6_veqw_xor>; 463defm : T_QVV_pat <V6_vgtb_xor, int_hexagon_V6_vgtb_xor>; 464defm : T_QVV_pat <V6_vgth_xor, int_hexagon_V6_vgth_xor>; 465defm : T_QVV_pat <V6_vgtw_xor, int_hexagon_V6_vgtw_xor>; 466defm : T_QVV_pat <V6_vgtub_xor, int_hexagon_V6_vgtub_xor>; 467defm : T_QVV_pat <V6_vgtuh_xor, int_hexagon_V6_vgtuh_xor>; 468defm : T_QVV_pat <V6_vgtuw_xor, int_hexagon_V6_vgtuw_xor>; 469 470defm : T_VV_pat <V6_vminub, int_hexagon_V6_vminub>; 471defm : T_VV_pat <V6_vminuh, int_hexagon_V6_vminuh>; 472defm : T_VV_pat <V6_vminh, int_hexagon_V6_vminh>; 473defm : T_VV_pat <V6_vminw, int_hexagon_V6_vminw>; 474defm : T_VV_pat <V6_vmaxub, int_hexagon_V6_vmaxub>; 475defm : T_VV_pat <V6_vmaxuh, int_hexagon_V6_vmaxuh>; 476defm : T_VV_pat <V6_vmaxh, int_hexagon_V6_vmaxh>; 477defm : T_VV_pat <V6_vmaxw, int_hexagon_V6_vmaxw>; 478defm : T_VV_pat <V6_vdelta, int_hexagon_V6_vdelta>; 479defm : T_VV_pat <V6_vrdelta, int_hexagon_V6_vrdelta>; 480defm : T_VV_pat <V6_vdealb4w, int_hexagon_V6_vdealb4w>; 481defm : T_VV_pat <V6_vmpyowh_rnd, int_hexagon_V6_vmpyowh_rnd>; 482defm : T_VV_pat <V6_vshuffeb, int_hexagon_V6_vshuffeb>; 483defm : T_VV_pat <V6_vshuffob, int_hexagon_V6_vshuffob>; 484defm : T_VV_pat <V6_vshufeh, int_hexagon_V6_vshufeh>; 485defm : T_VV_pat <V6_vshufoh, int_hexagon_V6_vshufoh>; 486defm : T_VV_pat <V6_vshufoeh, int_hexagon_V6_vshufoeh>; 487defm : T_VV_pat <V6_vshufoeb, int_hexagon_V6_vshufoeb>; 488defm : T_VV_pat <V6_vcombine, int_hexagon_V6_vcombine>; 489defm : T_VV_pat <V6_vmpyieoh, int_hexagon_V6_vmpyieoh>; 490defm : T_VV_pat <V6_vsathub, int_hexagon_V6_vsathub>; 491defm : T_VV_pat <V6_vsatwh, int_hexagon_V6_vsatwh>; 492defm : T_VV_pat <V6_vroundwh, int_hexagon_V6_vroundwh>; 493defm : T_VV_pat <V6_vroundwuh, int_hexagon_V6_vroundwuh>; 494defm : T_VV_pat <V6_vroundhb, int_hexagon_V6_vroundhb>; 495defm : T_VV_pat <V6_vroundhub, int_hexagon_V6_vroundhub>; 496defm : T_VV_pat <V6_vasrwv, int_hexagon_V6_vasrwv>; 497defm : T_VV_pat <V6_vlsrwv, int_hexagon_V6_vlsrwv>; 498defm : T_VV_pat <V6_vlsrhv, int_hexagon_V6_vlsrhv>; 499defm : T_VV_pat <V6_vasrhv, int_hexagon_V6_vasrhv>; 500defm : T_VV_pat <V6_vaslwv, int_hexagon_V6_vaslwv>; 501defm : T_VV_pat <V6_vaslhv, int_hexagon_V6_vaslhv>; 502defm : T_VV_pat <V6_vaddb, int_hexagon_V6_vaddb>; 503defm : T_VV_pat <V6_vaddh, int_hexagon_V6_vaddh>; 504defm : T_VV_pat <V6_vmpyiewuh, int_hexagon_V6_vmpyiewuh>; 505defm : T_VV_pat <V6_vmpyiowh, int_hexagon_V6_vmpyiowh>; 506defm : T_VV_pat <V6_vpackeb, int_hexagon_V6_vpackeb>; 507defm : T_VV_pat <V6_vpackeh, int_hexagon_V6_vpackeh>; 508defm : T_VV_pat <V6_vpackhub_sat, int_hexagon_V6_vpackhub_sat>; 509defm : T_VV_pat <V6_vpackhb_sat, int_hexagon_V6_vpackhb_sat>; 510defm : T_VV_pat <V6_vpackwuh_sat, int_hexagon_V6_vpackwuh_sat>; 511defm : T_VV_pat <V6_vpackwh_sat, int_hexagon_V6_vpackwh_sat>; 512defm : T_VV_pat <V6_vpackob, int_hexagon_V6_vpackob>; 513defm : T_VV_pat <V6_vpackoh, int_hexagon_V6_vpackoh>; 514defm : T_VV_pat <V6_vmpyewuh, int_hexagon_V6_vmpyewuh>; 515defm : T_VV_pat <V6_vmpyowh, int_hexagon_V6_vmpyowh>; 516 517defm : T_QVV_pat <V6_vaddbq, int_hexagon_V6_vaddbq>; 518defm : T_QVV_pat <V6_vaddhq, int_hexagon_V6_vaddhq>; 519defm : T_QVV_pat <V6_vaddwq, int_hexagon_V6_vaddwq>; 520defm : T_QVV_pat <V6_vaddbnq, int_hexagon_V6_vaddbnq>; 521defm : T_QVV_pat <V6_vaddhnq, int_hexagon_V6_vaddhnq>; 522defm : T_QVV_pat <V6_vaddwnq, int_hexagon_V6_vaddwnq>; 523defm : T_QVV_pat <V6_vsubbq, int_hexagon_V6_vsubbq>; 524defm : T_QVV_pat <V6_vsubhq, int_hexagon_V6_vsubhq>; 525defm : T_QVV_pat <V6_vsubwq, int_hexagon_V6_vsubwq>; 526defm : T_QVV_pat <V6_vsubbnq, int_hexagon_V6_vsubbnq>; 527defm : T_QVV_pat <V6_vsubhnq, int_hexagon_V6_vsubhnq>; 528defm : T_QVV_pat <V6_vsubwnq, int_hexagon_V6_vsubwnq>; 529 530defm : T_V_pat <V6_vabsh, int_hexagon_V6_vabsh>; 531defm : T_V_pat <V6_vabsw, int_hexagon_V6_vabsw>; 532defm : T_V_pat <V6_vabsw_sat, int_hexagon_V6_vabsw_sat>; 533defm : T_V_pat <V6_vabsh_sat, int_hexagon_V6_vabsh_sat>; 534defm : T_V_pat <V6_vnot, int_hexagon_V6_vnot>; 535defm : T_V_pat <V6_vassign, int_hexagon_V6_vassign>; 536defm : T_V_pat <V6_vzb, int_hexagon_V6_vzb>; 537defm : T_V_pat <V6_vzh, int_hexagon_V6_vzh>; 538defm : T_V_pat <V6_vsb, int_hexagon_V6_vsb>; 539defm : T_V_pat <V6_vsh, int_hexagon_V6_vsh>; 540defm : T_V_pat <V6_vdealh, int_hexagon_V6_vdealh>; 541defm : T_V_pat <V6_vdealb, int_hexagon_V6_vdealb>; 542defm : T_V_pat <V6_vunpackub, int_hexagon_V6_vunpackub>; 543defm : T_V_pat <V6_vunpackuh, int_hexagon_V6_vunpackuh>; 544defm : T_V_pat <V6_vunpackb, int_hexagon_V6_vunpackb>; 545defm : T_V_pat <V6_vunpackh, int_hexagon_V6_vunpackh>; 546defm : T_V_pat <V6_vshuffh, int_hexagon_V6_vshuffh>; 547defm : T_V_pat <V6_vshuffb, int_hexagon_V6_vshuffb>; 548defm : T_V_pat <V6_vcl0w, int_hexagon_V6_vcl0w>; 549defm : T_V_pat <V6_vpopcounth, int_hexagon_V6_vpopcounth>; 550defm : T_V_pat <V6_vcl0h, int_hexagon_V6_vcl0h>; 551defm : T_V_pat <V6_vnormamtw, int_hexagon_V6_vnormamtw>; 552defm : T_V_pat <V6_vnormamth, int_hexagon_V6_vnormamth>; 553 554defm : T_W_pat <V6_lo, int_hexagon_V6_lo>; 555defm : T_W_pat <V6_hi, int_hexagon_V6_hi>; 556defm : T_W_pat <V6_vassignp, int_hexagon_V6_vassignp>; 557 558defm : T_WRI_pat <V6_vrmpybusi, int_hexagon_V6_vrmpybusi>; 559defm : T_WRI_pat <V6_vrsadubi, int_hexagon_V6_vrsadubi>; 560defm : T_WRI_pat <V6_vrmpyubi, int_hexagon_V6_vrmpyubi>; 561 562defm : T_WWRI_pat <V6_vrmpybusi_acc, int_hexagon_V6_vrmpybusi_acc>; 563defm : T_WWRI_pat <V6_vrsadubi_acc, int_hexagon_V6_vrsadubi_acc>; 564defm : T_WWRI_pat <V6_vrmpyubi_acc, int_hexagon_V6_vrmpyubi_acc>; 565 566// assembler mapped. 567//defm : T_V_pat <V6_vtran2x2, int_hexagon_V6_vtran2x2>; 568// not present earlier.. need to add intrinsic 569defm : T_VVR_pat <V6_valignb, int_hexagon_V6_valignb>; 570defm : T_VVR_pat <V6_vlalignb, int_hexagon_V6_vlalignb>; 571defm : T_VVR_pat <V6_vasrwh, int_hexagon_V6_vasrwh>; 572defm : T_VVR_pat <V6_vasrwhsat, int_hexagon_V6_vasrwhsat>; 573defm : T_VVR_pat <V6_vasrwhrndsat, int_hexagon_V6_vasrwhrndsat>; 574defm : T_VVR_pat <V6_vasrwuhsat, int_hexagon_V6_vasrwuhsat>; 575defm : T_VVR_pat <V6_vasrhubsat, int_hexagon_V6_vasrhubsat>; 576defm : T_VVR_pat <V6_vasrhubrndsat, int_hexagon_V6_vasrhubrndsat>; 577defm : T_VVR_pat <V6_vasrhbrndsat, int_hexagon_V6_vasrhbrndsat>; 578 579defm : T_VVR_pat <V6_vshuffvdd, int_hexagon_V6_vshuffvdd>; 580defm : T_VVR_pat <V6_vdealvdd, int_hexagon_V6_vdealvdd>; 581 582defm : T_WV_pat <V6_vunpackob, int_hexagon_V6_vunpackob>; 583defm : T_WV_pat <V6_vunpackoh, int_hexagon_V6_vunpackoh>; 584defm : T_VVI_pat <V6_valignbi, int_hexagon_V6_valignbi>; 585defm : T_VVI_pat <V6_vlalignbi, int_hexagon_V6_vlalignbi>; 586 587defm : T_QVV_pat <V6_vswap, int_hexagon_V6_vswap>; 588defm : T_QVV_pat <V6_vmux, int_hexagon_V6_vmux>; 589defm : T_QQ_pat <V6_pred_and, int_hexagon_V6_pred_and>; 590defm : T_QQ_pat <V6_pred_or, int_hexagon_V6_pred_or>; 591defm : T_Q_pat <V6_pred_not, int_hexagon_V6_pred_not>; 592defm : T_QQ_pat <V6_pred_xor, int_hexagon_V6_pred_xor>; 593defm : T_QQ_pat <V6_pred_or_n, int_hexagon_V6_pred_or_n>; 594defm : T_QQ_pat <V6_pred_and_n, int_hexagon_V6_pred_and_n>; 595defm : T_VV_pat <V6_veqb, int_hexagon_V6_veqb>; 596defm : T_VV_pat <V6_veqh, int_hexagon_V6_veqh>; 597defm : T_VV_pat <V6_veqw, int_hexagon_V6_veqw>; 598defm : T_VV_pat <V6_vgtb, int_hexagon_V6_vgtb>; 599defm : T_VV_pat <V6_vgth, int_hexagon_V6_vgth>; 600defm : T_VV_pat <V6_vgtw, int_hexagon_V6_vgtw>; 601defm : T_VV_pat <V6_vgtub, int_hexagon_V6_vgtub>; 602defm : T_VV_pat <V6_vgtuh, int_hexagon_V6_vgtuh>; 603defm : T_VV_pat <V6_vgtuw, int_hexagon_V6_vgtuw>; 604 605defm : T_VQR_pat <V6_vandqrt_acc, int_hexagon_V6_vandqrt_acc>; 606defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>; 607defm : T_QR_pat <V6_vandqrt, int_hexagon_V6_vandqrt>; 608defm : T_R_pat <V6_lvsplatw, int_hexagon_V6_lvsplatw>; 609defm : T_R_pat <V6_pred_scalar2, int_hexagon_V6_pred_scalar2>; 610defm : T_VR_pat <V6_vandvrt, int_hexagon_V6_vandvrt>; 611 612defm : T_VVR_pat <V6_vlutvvb, int_hexagon_V6_vlutvvb>; 613defm : T_VVR_pat <V6_vlutvwh, int_hexagon_V6_vlutvwh>; 614defm : T_VVVR_pat <V6_vlutvvb_oracc, int_hexagon_V6_vlutvvb_oracc>; 615defm : T_WVVR_pat <V6_vlutvwh_oracc, int_hexagon_V6_vlutvwh_oracc>; 616 617defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>; 618def : T_PI_pat <S6_rol_i_p, int_hexagon_S6_rol_i_p>; 619def : T_RI_pat <S6_rol_i_r, int_hexagon_S6_rol_i_r>; 620def : T_PPI_pat <S6_rol_i_p_nac, int_hexagon_S6_rol_i_p_nac>; 621def : T_PPI_pat <S6_rol_i_p_acc, int_hexagon_S6_rol_i_p_acc>; 622def : T_PPI_pat <S6_rol_i_p_and, int_hexagon_S6_rol_i_p_and>; 623def : T_PPI_pat <S6_rol_i_p_or, int_hexagon_S6_rol_i_p_or>; 624def : T_PPI_pat <S6_rol_i_p_xacc, int_hexagon_S6_rol_i_p_xacc>; 625def : T_RRI_pat <S6_rol_i_r_nac, int_hexagon_S6_rol_i_r_nac>; 626def : T_RRI_pat <S6_rol_i_r_acc, int_hexagon_S6_rol_i_r_acc>; 627def : T_RRI_pat <S6_rol_i_r_and, int_hexagon_S6_rol_i_r_and>; 628def : T_RRI_pat <S6_rol_i_r_or, int_hexagon_S6_rol_i_r_or>; 629def : T_RRI_pat <S6_rol_i_r_xacc, int_hexagon_S6_rol_i_r_xacc>; 630 631defm : T_VR_pat <V6_extractw, int_hexagon_V6_extractw>; 632defm : T_VR_pat <V6_vinsertwr, int_hexagon_V6_vinsertwr>; 633 634//def : T_PPQ_pat <S2_cabacencbin, int_hexagon_S2_cabacencbin>; 635 636def: Pat<(v64i16 (trunc v64i32:$Vdd)), 637 (v64i16 (V6_vpackwh_sat 638 (v32i32 (V6_hi HvxWR:$Vdd)), 639 (v32i32 (V6_lo HvxWR:$Vdd))))>; 640 641def: Pat<(int_hexagon_V6_vd0), (V6_vd0)>; 642def: Pat<(int_hexagon_V6_vd0_128B), (V6_vd0)>; 643 644