• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
4
5---
6name: and_ss
7legalized: true
8
9body: |
10  bb.0:
11    liveins: $sgpr0, $sgpr1
12    ; CHECK-LABEL: name: and_ss
13    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
14    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
15    ; CHECK: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY]], [[COPY1]]
16    %0:_(s32) = COPY $sgpr0
17    %1:_(s32) = COPY $sgpr1
18    %2:_(s32) = G_AND %0, %1
19...
20
21---
22name: and_sv
23legalized: true
24
25body: |
26  bb.0:
27    liveins: $sgpr0, $vgpr0
28    ; CHECK-LABEL: name: and_sv
29    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
30    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
31    ; CHECK: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[COPY1]]
32    %0:_(s32) = COPY $sgpr0
33    %1:_(s32) = COPY $vgpr0
34    %2:_(s32) = G_AND %0, %1
35...
36
37---
38name: and_vs
39legalized: true
40
41body: |
42  bb.0:
43    liveins: $sgpr0, $vgpr0
44    ; CHECK-LABEL: name: and_vs
45    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
46    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
47    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
48    ; CHECK: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[COPY2]]
49    %0:_(s32) = COPY $vgpr0
50    %1:_(s32) = COPY $sgpr0
51    %2:_(s32) = G_AND %0, %1
52...
53
54---
55name: and_vv
56legalized: true
57
58body: |
59  bb.0:
60    liveins: $vgpr0, $vgpr1
61    ; CHECK-LABEL: name: and_vv
62    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
63    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
64    ; CHECK: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[COPY1]]
65    %0:_(s32) = COPY $vgpr0
66    %1:_(s32) = COPY $vgpr1
67    %2:_(s32) = G_AND %0, %1
68...
69