1; RUN: llc -mtriple thumbv7--windows-itanium -filetype asm -o - %s | FileCheck %s 2 3declare double @llvm.powi.f64(double, i32) 4declare float @llvm.powi.f32(float, i32) 5 6define arm_aapcs_vfpcc double @d(double %d, i32 %i) { 7entry: 8 %0 = tail call double @llvm.powi.f64(double %d, i32 %i) 9 ret double %0 10} 11 12; CHECK-LABEL: d: 13; CHECK: vmov s[[REGISTER:[0-9]+]], r0 14; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]] 15; CHECK-NEXT: b pow 16; CHECK-NOT: __powisf2 17 18define arm_aapcs_vfpcc float @f(float %f, i32 %i) { 19entry: 20 %0 = tail call float @llvm.powi.f32(float %f, i32 %i) 21 ret float %0 22} 23 24; CHECK-LABEL: f: 25; CHECK: vmov s[[REGISTER:[0-9]+]], r0 26; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]] 27; CHECK-NEXT: b pow 28; CHECK-NOT: __powisf2 29 30define arm_aapcs_vfpcc float @g(double %d, i32 %i) { 31entry: 32 %0 = tail call double @llvm.powi.f64(double %d, i32 %i) 33 %conv = fptrunc double %0 to float 34 ret float %conv 35} 36 37; CHECK-LABEL: g: 38; CHECK: vmov s[[REGISTER:[0-9]+]], r0 39; CHECK-NEXT: vcvt.f64.s32 d1, s[[REGISTER]] 40; CHECK-NEXT: bl pow 41; CHECK-NOT: bl __powidf2 42; CHECK-NEXT: vcvt.f32.f64 s0, d0 43 44define arm_aapcs_vfpcc double @h(float %f, i32 %i) { 45entry: 46 %0 = tail call float @llvm.powi.f32(float %f, i32 %i) 47 %conv = fpext float %0 to double 48 ret double %conv 49} 50 51; CHECK-LABEL: h: 52; CHECK: vmov s[[REGISTER:[0-9]+]], r0 53; CHECK-NEXT: vcvt.f32.s32 s1, s[[REGISTER]] 54; CHECK-NEXT: bl powf 55; CHECK-NOT: bl __powisf2 56; CHECK-NEXT: vcvt.f64.f32 d0, s0 57 58