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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Keystone2: pll initialization
4  *
5  * (C) Copyright 2012-2014
6  *     Texas Instruments Incorporated, <www.ti.com>
7  */
8 
9 #include <common.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/clock_defs.h>
12 
13 /* DEV and ARM speed definitions as specified in DEVSPEED register */
14 int __weak speeds[DEVSPEED_NUMSPDS] = {
15 	SPD1000,
16 	SPD1200,
17 	SPD1350,
18 	SPD1400,
19 	SPD1500,
20 	SPD1400,
21 	SPD1350,
22 	SPD1200,
23 	SPD1000,
24 	SPD800,
25 };
26 
27 const struct keystone_pll_regs keystone_pll_regs[] = {
28 	[CORE_PLL]	= {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
29 	[PASS_PLL]	= {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
30 	[TETRIS_PLL]	= {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
31 	[DDR3A_PLL]	= {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
32 	[DDR3B_PLL]	= {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
33 	[UART_PLL]	= {KS2_UARTPLLCTL0, KS2_UARTPLLCTL1},
34 };
35 
pll_pa_clk_sel(void)36 inline void pll_pa_clk_sel(void)
37 {
38 	setbits_le32(keystone_pll_regs[PASS_PLL].reg1, CFG_PLLCTL1_PAPLL_MASK);
39 }
40 
wait_for_completion(const struct pll_init_data * data)41 static void wait_for_completion(const struct pll_init_data *data)
42 {
43 	int i;
44 	for (i = 0; i < 100; i++) {
45 		sdelay(450);
46 		if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK))
47 			break;
48 	}
49 }
50 
bypass_main_pll(const struct pll_init_data * data)51 static inline void bypass_main_pll(const struct pll_init_data *data)
52 {
53 	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK |
54 			   PLLCTL_PLLEN_MASK);
55 
56 	/* 4 cycles of reference clock CLKIN*/
57 	sdelay(340);
58 }
59 
configure_mult_div(const struct pll_init_data * data)60 static void configure_mult_div(const struct pll_init_data *data)
61 {
62 	u32 pllm, plld, bwadj;
63 
64 	pllm = data->pll_m - 1;
65 	plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK;
66 
67 	/* Program Multiplier */
68 	if (data->pll == MAIN_PLL)
69 		pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
70 
71 	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
72 			CFG_PLLCTL0_PLLM_MASK,
73 			pllm << CFG_PLLCTL0_PLLM_SHIFT);
74 
75 	/* Program BWADJ */
76 	bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */
77 	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
78 			CFG_PLLCTL0_BWADJ_MASK,
79 			(bwadj << CFG_PLLCTL0_BWADJ_SHIFT) &
80 			CFG_PLLCTL0_BWADJ_MASK);
81 	bwadj = bwadj >> CFG_PLLCTL0_BWADJ_BITS;
82 	clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
83 			CFG_PLLCTL1_BWADJ_MASK, bwadj);
84 
85 	/* Program Divider */
86 	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
87 			CFG_PLLCTL0_PLLD_MASK, plld);
88 }
89 
configure_main_pll(const struct pll_init_data * data)90 void configure_main_pll(const struct pll_init_data *data)
91 {
92 	u32 tmp, pllod, i, alnctl_val = 0;
93 	u32 *offset;
94 
95 	pllod = data->pll_od - 1;
96 
97 	/* 100 micro sec for stabilization */
98 	sdelay(210000);
99 
100 	tmp = pllctl_reg_read(data->pll, secctl);
101 
102 	/* Check for Bypass */
103 	if (tmp & SECCTL_BYPASS_MASK) {
104 		setbits_le32(keystone_pll_regs[data->pll].reg1,
105 			     CFG_PLLCTL1_ENSAT_MASK);
106 
107 		bypass_main_pll(data);
108 
109 		/* Powerdown and powerup Main Pll */
110 		pllctl_reg_setbits(data->pll, secctl, SECCTL_BYPASS_MASK);
111 		pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);
112 		/* 5 micro sec */
113 		sdelay(21000);
114 
115 		pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);
116 	} else {
117 		bypass_main_pll(data);
118 	}
119 
120 	configure_mult_div(data);
121 
122 	/* Program Output Divider */
123 	pllctl_reg_rmw(data->pll, secctl, SECCTL_OP_DIV_MASK,
124 		       ((pllod << SECCTL_OP_DIV_SHIFT) & SECCTL_OP_DIV_MASK));
125 
126 	/* Program PLLDIVn */
127 	wait_for_completion(data);
128 	for (i = 0; i < PLLDIV_MAX; i++) {
129 		if (i < 3)
130 			offset = pllctl_reg(data->pll, div1) + i;
131 		else
132 			offset = pllctl_reg(data->pll, div4) + (i - 3);
133 
134 		if (divn_val[i] != -1) {
135 			__raw_writel(divn_val[i] | PLLDIV_ENABLE_MASK, offset);
136 			alnctl_val |= BIT(i);
137 		}
138 	}
139 
140 	if (alnctl_val) {
141 		pllctl_reg_setbits(data->pll, alnctl, alnctl_val);
142 		/*
143 		 * Set GOSET bit in PLLCMD to initiate the GO operation
144 		 * to change the divide
145 		 */
146 		pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GOSTAT_MASK);
147 		wait_for_completion(data);
148 	}
149 
150 	/* Reset PLL */
151 	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK);
152 	sdelay(21000);	/* Wait for a minimum of 7 us*/
153 	pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK);
154 	sdelay(105000);	/* Wait for PLL Lock time (min 50 us) */
155 
156 	/* Enable PLL */
157 	pllctl_reg_clrbits(data->pll, secctl, SECCTL_BYPASS_MASK);
158 	pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK);
159 }
160 
configure_secondary_pll(const struct pll_init_data * data)161 void configure_secondary_pll(const struct pll_init_data *data)
162 {
163 	int pllod = data->pll_od - 1;
164 
165 	/* Enable Glitch free bypass for ARM PLL */
166 	if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
167 		clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
168 
169 	/* Enable Bypass mode */
170 	setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK);
171 	setbits_le32(keystone_pll_regs[data->pll].reg0,
172 		     CFG_PLLCTL0_BYPASS_MASK);
173 
174 	configure_mult_div(data);
175 
176 	/* Program Output Divider */
177 	clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
178 			CFG_PLLCTL0_CLKOD_MASK,
179 			(pllod << CFG_PLLCTL0_CLKOD_SHIFT) &
180 			CFG_PLLCTL0_CLKOD_MASK);
181 
182 	/* Reset PLL */
183 	setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
184 	/* Wait for 5 micro seconds */
185 	sdelay(21000);
186 
187 	/* Select the Output of PASS PLL as input to PASS */
188 	if (data->pll == PASS_PLL && cpu_is_k2hk())
189 		pll_pa_clk_sel();
190 
191 	clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
192 	/* Wait for 500 * REFCLK cucles * (PLLD + 1) */
193 	sdelay(105000);
194 
195 	/* Switch to PLL mode */
196 	clrbits_le32(keystone_pll_regs[data->pll].reg0,
197 		     CFG_PLLCTL0_BYPASS_MASK);
198 
199 	/* Select the Output of ARM PLL as input to ARM */
200 	if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
201 		setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
202 }
203 
init_pll(const struct pll_init_data * data)204 void init_pll(const struct pll_init_data *data)
205 {
206 	if (data->pll == MAIN_PLL)
207 		configure_main_pll(data);
208 	else
209 		configure_secondary_pll(data);
210 
211 	/*
212 	 * This is required to provide a delay between multiple
213 	 * consequent PPL configurations
214 	 */
215 	sdelay(210000);
216 }
217 
init_plls(void)218 void init_plls(void)
219 {
220 	struct pll_init_data *data;
221 	int pll;
222 
223 	for (pll = MAIN_PLL; pll < MAX_PLL_COUNT; pll++) {
224 		data = get_pll_init_data(pll);
225 		if (data)
226 			init_pll(data);
227 	}
228 }
229 
get_max_speed(u32 val,u32 speed_supported,int * spds)230 static int get_max_speed(u32 val, u32 speed_supported, int *spds)
231 {
232 	int speed;
233 
234 	/* Left most setbit gives the speed */
235 	for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) {
236 		if ((val & BIT(speed)) & speed_supported)
237 			return spds[speed];
238 	}
239 
240 	/* If no bit is set, return minimum speed */
241 	if (cpu_is_k2g())
242 		return SPD200;
243 	else
244 		return SPD800;
245 }
246 
read_efuse_bootrom(void)247 static inline u32 read_efuse_bootrom(void)
248 {
249 	if (cpu_is_k2hk() && (cpu_revision() <= 1))
250 		return __raw_readl(KS2_REV1_DEVSPEED);
251 	else
252 		return __raw_readl(KS2_EFUSE_BOOTROM);
253 }
254 
get_max_arm_speed(int * spds)255 int get_max_arm_speed(int *spds)
256 {
257 	u32 armspeed = read_efuse_bootrom();
258 
259 	armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >>
260 		    DEVSPEED_ARMSPEED_SHIFT;
261 
262 	return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS, spds);
263 }
264 
get_max_dev_speed(int * spds)265 int get_max_dev_speed(int *spds)
266 {
267 	u32 devspeed = read_efuse_bootrom();
268 
269 	devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >>
270 		    DEVSPEED_DEVSPEED_SHIFT;
271 
272 	return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS, spds);
273 }
274 
275 /**
276  * pll_freq_get - get pll frequency
277  * @pll:	pll identifier
278  */
pll_freq_get(int pll)279 static unsigned long pll_freq_get(int pll)
280 {
281 	unsigned long mult = 1, prediv = 1, output_div = 2;
282 	unsigned long ret;
283 	u32 tmp, reg;
284 
285 	if (pll == MAIN_PLL) {
286 		ret = get_external_clk(sys_clk);
287 		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) {
288 			/* PLL mode */
289 			tmp = __raw_readl(KS2_MAINPLLCTL0);
290 			prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;
291 			mult = ((tmp & CFG_PLLCTL0_PLLM_HI_MASK) >>
292 				CFG_PLLCTL0_PLLM_SHIFT |
293 				(pllctl_reg_read(pll, mult) &
294 				 PLLM_MULT_LO_MASK)) + 1;
295 			output_div = ((pllctl_reg_read(pll, secctl) &
296 				       SECCTL_OP_DIV_MASK) >>
297 				       SECCTL_OP_DIV_SHIFT) + 1;
298 
299 			ret = ret / prediv / output_div * mult;
300 		}
301 	} else {
302 		switch (pll) {
303 		case PASS_PLL:
304 			ret = get_external_clk(pa_clk);
305 			reg = KS2_PASSPLLCTL0;
306 			break;
307 		case TETRIS_PLL:
308 			ret = get_external_clk(tetris_clk);
309 			reg = KS2_ARMPLLCTL0;
310 			break;
311 		case DDR3A_PLL:
312 			ret = get_external_clk(ddr3a_clk);
313 			reg = KS2_DDR3APLLCTL0;
314 			break;
315 		case DDR3B_PLL:
316 			ret = get_external_clk(ddr3b_clk);
317 			reg = KS2_DDR3BPLLCTL0;
318 			break;
319 		case UART_PLL:
320 			ret = get_external_clk(uart_clk);
321 			reg = KS2_UARTPLLCTL0;
322 			break;
323 		default:
324 			return 0;
325 		}
326 
327 		tmp = __raw_readl(reg);
328 
329 		if (!(tmp & CFG_PLLCTL0_BYPASS_MASK)) {
330 			/* Bypass disabled */
331 			prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;
332 			mult = ((tmp & CFG_PLLCTL0_PLLM_MASK) >>
333 				CFG_PLLCTL0_PLLM_SHIFT) + 1;
334 			output_div = ((tmp & CFG_PLLCTL0_CLKOD_MASK) >>
335 				      CFG_PLLCTL0_CLKOD_SHIFT) + 1;
336 			ret = ((ret / prediv) * mult) / output_div;
337 		}
338 	}
339 
340 	return ret;
341 }
342 
ks_clk_get_rate(unsigned int clk)343 unsigned long ks_clk_get_rate(unsigned int clk)
344 {
345 	unsigned long freq = 0;
346 
347 	switch (clk) {
348 	case core_pll_clk:
349 		freq = pll_freq_get(CORE_PLL);
350 		break;
351 	case pass_pll_clk:
352 		freq = pll_freq_get(PASS_PLL);
353 		break;
354 	case tetris_pll_clk:
355 		if (!cpu_is_k2e())
356 			freq = pll_freq_get(TETRIS_PLL);
357 		break;
358 	case ddr3a_pll_clk:
359 		freq = pll_freq_get(DDR3A_PLL);
360 		break;
361 	case ddr3b_pll_clk:
362 		if (cpu_is_k2hk())
363 			freq = pll_freq_get(DDR3B_PLL);
364 		break;
365 	case uart_pll_clk:
366 		if (cpu_is_k2g())
367 			freq = pll_freq_get(UART_PLL);
368 		break;
369 	case sys_clk0_1_clk:
370 	case sys_clk0_clk:
371 		freq = pll_freq_get(CORE_PLL) / pll0div_read(1);
372 		break;
373 	case sys_clk1_clk:
374 	return pll_freq_get(CORE_PLL) / pll0div_read(2);
375 		break;
376 	case sys_clk2_clk:
377 		freq = pll_freq_get(CORE_PLL) / pll0div_read(3);
378 		break;
379 	case sys_clk3_clk:
380 		freq = pll_freq_get(CORE_PLL) / pll0div_read(4);
381 		break;
382 	case sys_clk0_2_clk:
383 		freq = ks_clk_get_rate(sys_clk0_clk) / 2;
384 		break;
385 	case sys_clk0_3_clk:
386 		freq = ks_clk_get_rate(sys_clk0_clk) / 3;
387 		break;
388 	case sys_clk0_4_clk:
389 		freq = ks_clk_get_rate(sys_clk0_clk) / 4;
390 		break;
391 	case sys_clk0_6_clk:
392 		freq = ks_clk_get_rate(sys_clk0_clk) / 6;
393 		break;
394 	case sys_clk0_8_clk:
395 		freq = ks_clk_get_rate(sys_clk0_clk) / 8;
396 		break;
397 	case sys_clk0_12_clk:
398 		freq = ks_clk_get_rate(sys_clk0_clk) / 12;
399 		break;
400 	case sys_clk0_24_clk:
401 		freq = ks_clk_get_rate(sys_clk0_clk) / 24;
402 		break;
403 	case sys_clk1_3_clk:
404 		freq = ks_clk_get_rate(sys_clk1_clk) / 3;
405 		break;
406 	case sys_clk1_4_clk:
407 		freq = ks_clk_get_rate(sys_clk1_clk) / 4;
408 		break;
409 	case sys_clk1_6_clk:
410 		freq = ks_clk_get_rate(sys_clk1_clk) / 6;
411 		break;
412 	case sys_clk1_12_clk:
413 		freq = ks_clk_get_rate(sys_clk1_clk) / 12;
414 		break;
415 	default:
416 		break;
417 	}
418 
419 	return freq;
420 }
421