README
1Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards
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3
41. Board Description
5
6 The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring
7 the Freescale MPC8349E processor in a Mini-ITX form factor.
8
9 The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences:
10
11 A) One 8MB on-board flash EEPROM chip, instead of two.
12 B) No SATA controller
13 C) No Compact Flash slot
14 D) No Mini-PCI slot
15 E) No Vitesse 7385 5-port Ethernet switch
16 F) No 4-port USB Type-A interface
17
182. Board Switches and Jumpers
19
202.0 Descriptions for all of the board jumpers can be found in the User
21 Guide. Of particular interest to U-Boot developers is jumper J22:
22
23 Pos. Name Default Description
24 -----------------------------------------------------------------------
25 A LGPL0 ON (0) HRCW source, bit 0
26 B LGPL1 ON (0) HRCW source, bit 1
27 C LGPL3 ON (0) HRCW source, bit 2
28 D LGPL5 OFF (1) PCI_SYNC_OUT frequency
29 E BOOT1 ON (0) Flash EEPROM boot device
30 F PCI_M66EN ON (0) PCI 66MHz enable
31 G I2C-WP ON (0) I2C EEPROM write protection
32 H F_WP OFF (1) Flash EEPROM write protection
33
34 Jumper J22.E is only for the ITX, and it decides the configuration
35 of the flash chips. If J22.E is ON (i.e. jumpered), then flash chip
36 U4 is located at address FE000000 and flash chip U7 is at FE800000.
37 If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000.
38
39 For U-Boot development, J22.E can be used to switch back-and-forth
40 between two U-Boot images.
41
423. Memory Map
43
443.1. The memory map should look pretty much like this:
45
46 0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB)
47 0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB)
48 0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB)
49 0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB)
50 0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB)
51 0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB)
52 0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only)
53 0xF001_0000 - 0xF001_FFFF Local bus expansion slot
54 0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only)
55 0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory
56 0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only)
57
583.2 Flash EEPROM layout.
59
60 On the ITX, jumper J22.E is used to determine which flash chips are
61 at which address. When J22.E is switched, addresses from FE000000
62 to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF.
63
64 On the ITX, at the normal boot address (aka HIGHBOOT):
65
66 FE00_0000 HRCW
67 FE70_0000 Alternative U-Boot image
68 FE80_0000 Alternative HRCW
69 FEF0_0000 U-Boot image
70 FEFF_FFFF End of flash
71
72 On the ITX, at the low boot address (LOWBOOT)
73
74 FE00_0000 HRCW and U-Boot image
75 FE04_0000 U-Boot environment variables
76 FE80_0000 Alternative HRCW and U-Boot image
77 FEFF_FFFF End of flash
78
79 On the ITX-GP, the only option is LOWBOOT and there is only one chip
80
81 FE00_0000 HRCW and U-Boot image
82 FE04_0000 U-Boot environment variables
83 F7FF_FFFF End of flash
84
854. Definitions
86
874.1 Explanation of NEW definitions in:
88
89 include/configs/MPC8349ITX.h
90
91 CONFIG_MPC83xx MPC83xx family
92 CONFIG_MPC8349 MPC8349 specific
93 CONFIG_MPC8349ITX MPC8349E-mITX
94
955. Compilation
96
97 Assuming you're using BASH shell:
98
99 export CROSS_COMPILE=your-cross-compile-prefix
100 cd u-boot
101 make distclean
102
103 make MPC8349ITX_config
104 or:
105 make MPC8349ITXGP_config
106 or:
107 make MPC8349ITX_LOWBOOT_config
108
109 make
110
1116. Downloading and Flashing Images
112
1136.1 Download via tftp:
114
115 tftp $loadaddr <uboot>
116
117 where "<uboot>" is the path and filename, on the TFTP server, of
118 the U-Boot image.
119
1206.1 Reflash U-Boot Image using U-Boot
121
122 setenv uboot <uboot>
123 run tftpflash
124
125 where "<uboot>" is the path and filename, on the TFTP server, of
126 the U-Boot image.
127
1286.2 Using the HRCW to switch between two different U-Boot images on the ITX
129
130 Because the ITX has 16MB of flash, it is possible to keep two U-Boot
131 images in flash, and use the HRCW to specify which one is to be used
132 when the board boots. This trick is especially effective with a
133 hardware debugger that can override the HRCW, such as the BDI-2000.
134
135 When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image
136 at address FE000000. When the BMS bit is 1, the ITX will boot the
137 image at address FEF00000.
138
139 Therefore, just put a U-Boot image at both FE000000 and FEF00000 and
140 change the BMS bit whenever you want to boot the other image.
141
142 Step-by-step instructions:
143
144 1) Build an ITX image to be loaded at FEF00000
145
146 make distclean
147 make MPC8349ITX_config
148 make
149
150 2) Take the u-boot.bin image and flash it at FEF00000.
151
152 tftp $loadaddr u-boot.bin
153 protect off all
154 erase FEF00000 +$filesize
155 cp.b $loadaddr FEF00000 $filesize
156
157 3) Build an ITX image to be loaded at FE000000
158
159 make distclean
160 make MPC8349ITX_LOWBOOT_config
161 make
162
163 4) Take the u-boot.bin image and flash it at FE000000.
164
165 tftp $loadaddr u-boot.bin
166 protect off FE000000 +$filesize
167 erase FE000000 +$filesize
168 cp.b $loadaddr FE000000 $filesize
169
170 The HRCW in flash is currently set to boot the image at FE000000.
171
172 If you have a hardware debugger, configure it to set the HRCW to
173 B460A000 04040000 if you want to boot the image at FEF00000, or set
174 it to B060A000 04040000 if you want to boot the image at FE000000.
175
176 To change the HRCW in flash to boot the image at FEF00000, use these
177 U-Boot commands:
178
179 cp.b FE000000 1000 10000 ; copy 1st flash sector to 1000
180 mw.b 1020 b4 8 ; modify BMS bit
181 protect off FE000000 +10000
182 erase FE000000 +10000
183 cp.b 1000 FE000000 10000
184
1857. Notes
186 1) The console baudrate for MPC8349EITX is 115200bps.
187