1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
4 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <miiphy.h>
10 #include <tpm-v1.h>
11 #include <asm/io.h>
12 #include <asm/arch/cpu.h>
13 #include <asm-generic/gpio.h>
14
15 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
16 #include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
17
18 #include "keyprogram.h"
19 #include "dt_helpers.h"
20 #include "hydra.h"
21 #include "ihs_phys.h"
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 #define ETH_PHY_CTRL_REG 0
26 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11
27 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
28
29 #define DB_GP_88F68XX_GPP_OUT_ENA_LOW 0x7fffffff
30 #define DB_GP_88F68XX_GPP_OUT_ENA_MID 0xffffefff
31
32 #define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
33 #define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x00001000
34 #define DB_GP_88F68XX_GPP_POL_LOW 0x0
35 #define DB_GP_88F68XX_GPP_POL_MID 0x0
36
37 /*
38 * Define the DDR layout / topology here in the board file. This will
39 * be used by the DDR3 init code in the SPL U-Boot version to configure
40 * the DDR3 controller.
41 */
42 static struct mv_ddr_topology_map ddr_topology_map = {
43 DEBUG_LEVEL_ERROR,
44 0x1, /* active interfaces */
45 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
46 { { { {0x1, 0, 0, 0},
47 {0x1, 0, 0, 0},
48 {0x1, 0, 0, 0},
49 {0x1, 0, 0, 0},
50 {0x1, 0, 0, 0} },
51 SPEED_BIN_DDR_1600K, /* speed_bin */
52 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
53 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
54 DDR_FREQ_533, /* frequency */
55 0, 0, /* cas_wl cas_l */
56 MV_DDR_TEMP_LOW, /* temperature */
57 MV_DDR_TIM_DEFAULT} }, /* timing */
58 BUS_MASK_32BIT, /* Busses mask */
59 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
60 { {0} }, /* raw spd data */
61 {0} /* timing parameters */
62
63 };
64
65 static struct serdes_map serdes_topology_map[] = {
66 {SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
67 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
68 /* SATA tx polarity is inverted */
69 {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1},
70 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
71 {DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
72 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
73 };
74
hws_board_topology_load(struct serdes_map ** serdes_map_array,u8 * count)75 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
76 {
77 *serdes_map_array = serdes_topology_map;
78 *count = ARRAY_SIZE(serdes_topology_map);
79 return 0;
80 }
81
board_pex_config(void)82 void board_pex_config(void)
83 {
84 #ifdef CONFIG_SPL_BUILD
85 uint k;
86 struct gpio_desc gpio = {};
87
88 if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
89 /* prepare FPGA reconfiguration */
90 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
91 dm_gpio_set_value(&gpio, 0);
92
93 /* give lunatic PCIe clock some time to stabilize */
94 mdelay(500);
95
96 /* start FPGA reconfiguration */
97 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN);
98 }
99
100 /* wait for FPGA done */
101 if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) {
102 for (k = 0; k < 20; ++k) {
103 if (dm_gpio_get_value(&gpio)) {
104 printf("FPGA done after %u rounds\n", k);
105 break;
106 }
107 mdelay(100);
108 }
109 }
110
111 /* disable FPGA reset */
112 if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) {
113 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
114 dm_gpio_set_value(&gpio, 1);
115 }
116
117 /* wait for FPGA ready */
118 if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) {
119 for (k = 0; k < 2; ++k) {
120 if (!dm_gpio_get_value(&gpio))
121 break;
122 mdelay(100);
123 }
124 }
125 #endif
126 }
127
mv_ddr_topology_map_get(void)128 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
129 {
130 return &ddr_topology_map;
131 }
132
board_early_init_f(void)133 int board_early_init_f(void)
134 {
135 #ifdef CONFIG_SPL_BUILD
136 /* Configure MPP */
137 writel(0x00111111, MVEBU_MPP_BASE + 0x00);
138 writel(0x40040000, MVEBU_MPP_BASE + 0x04);
139 writel(0x00466444, MVEBU_MPP_BASE + 0x08);
140 writel(0x00043300, MVEBU_MPP_BASE + 0x0c);
141 writel(0x44400000, MVEBU_MPP_BASE + 0x10);
142 writel(0x20000334, MVEBU_MPP_BASE + 0x14);
143 writel(0x40000000, MVEBU_MPP_BASE + 0x18);
144 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
145
146 /* Set GPP Out value */
147 writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
148 writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
149
150 /* Set GPP Polarity */
151 writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
152 writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
153
154 /* Set GPP Out Enable */
155 writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
156 writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
157 #endif
158
159 return 0;
160 }
161
board_init(void)162 int board_init(void)
163 {
164 /* Address of boot parameters */
165 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
166
167 return 0;
168 }
169
170 #ifndef CONFIG_SPL_BUILD
init_host_phys(struct mii_dev * bus)171 void init_host_phys(struct mii_dev *bus)
172 {
173 uint k;
174
175 for (k = 0; k < 2; ++k) {
176 struct phy_device *phydev;
177
178 phydev = phy_find_by_mask(bus, 1 << k,
179 PHY_INTERFACE_MODE_SGMII);
180
181 if (phydev)
182 phy_config(phydev);
183 }
184 }
185
ccdc_eth_init(void)186 int ccdc_eth_init(void)
187 {
188 uint k;
189 uint octo_phy_mask = 0;
190 int ret;
191 struct mii_dev *bus;
192
193 /* Init SoC's phys */
194 bus = miiphy_get_dev_by_name("ethernet@34000");
195
196 if (bus)
197 init_host_phys(bus);
198
199 bus = miiphy_get_dev_by_name("ethernet@70000");
200
201 if (bus)
202 init_host_phys(bus);
203
204 /* Init octo phys */
205 octo_phy_mask = calculate_octo_phy_mask();
206
207 printf("IHS PHYS: %08x", octo_phy_mask);
208
209 ret = init_octo_phys(octo_phy_mask);
210
211 if (ret)
212 return ret;
213
214 printf("\n");
215
216 if (!get_fpga()) {
217 puts("fpga was NULL\n");
218 return 1;
219 }
220
221 /* reset all FPGA-QSGMII instances */
222 for (k = 0; k < 80; ++k)
223 writel(1 << 31, get_fpga()->qsgmii_port_state[k]);
224
225 udelay(100);
226
227 for (k = 0; k < 80; ++k)
228 writel(0, get_fpga()->qsgmii_port_state[k]);
229 return 0;
230 }
231
232 #endif
233
board_late_init(void)234 int board_late_init(void)
235 {
236 #ifndef CONFIG_SPL_BUILD
237 hydra_initialize();
238 #endif
239 return 0;
240 }
241
board_fix_fdt(void * rw_fdt_blob)242 int board_fix_fdt(void *rw_fdt_blob)
243 {
244 struct udevice *bus = NULL;
245 uint k;
246 char name[64];
247 int err;
248
249 err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus);
250
251 if (err) {
252 printf("Could not get I2C bus.\n");
253 return err;
254 }
255
256 for (k = 0x21; k <= 0x26; k++) {
257 snprintf(name, 64,
258 "/soc/internal-regs/i2c@11000/pca9698@%02x", k);
259
260 if (!dm_i2c_simple_probe(bus, k))
261 fdt_disable_by_ofname(rw_fdt_blob, name);
262 }
263
264 return 0;
265 }
266
last_stage_init(void)267 int last_stage_init(void)
268 {
269 #ifndef CONFIG_SPL_BUILD
270 ccdc_eth_init();
271 #endif
272 if (tpm_init() || tpm_startup(TPM_ST_CLEAR) ||
273 tpm_continue_self_test()) {
274 return 1;
275 }
276
277 mdelay(37);
278
279 flush_keys();
280 load_and_run_keyprog();
281
282 return 0;
283 }
284