1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 */
6
7 #include <common.h>
8 #include <command.h>
9 #include <malloc.h>
10 #include <net.h>
11 #include <netdev.h>
12 #include <asm/cpm_8xx.h>
13 #include <asm/io.h>
14
15 #include <phy.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 /* define WANT_MII when MII support is required */
20 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
21 #define WANT_MII
22 #else
23 #undef WANT_MII
24 #endif
25
26 #if defined(WANT_MII)
27 #include <miiphy.h>
28
29 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
30 #error "CONFIG_MII has to be defined!"
31 #endif
32
33 #endif
34
35 #if defined(CONFIG_RMII) && !defined(WANT_MII)
36 #error RMII support is unusable without a working PHY.
37 #endif
38
39 #ifdef CONFIG_SYS_DISCOVER_PHY
40 static int mii_discover_phy(struct eth_device *dev);
41 #endif
42
43 int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg);
44 int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
45 u16 value);
46
47 static struct ether_fcc_info_s
48 {
49 int ether_index;
50 int fecp_offset;
51 int phy_addr;
52 int actual_phy_addr;
53 int initialized;
54 }
55 ether_fcc_info[] = {
56 #if defined(CONFIG_ETHER_ON_FEC1)
57 {
58 0,
59 offsetof(immap_t, im_cpm.cp_fec1),
60 CONFIG_FEC1_PHY,
61 -1,
62 0,
63
64 },
65 #endif
66 #if defined(CONFIG_ETHER_ON_FEC2)
67 {
68 1,
69 offsetof(immap_t, im_cpm.cp_fec2),
70 CONFIG_FEC2_PHY,
71 -1,
72 0,
73 },
74 #endif
75 };
76
77 /* Ethernet Transmit and Receive Buffers */
78 #define DBUF_LENGTH 1520
79
80 #define TX_BUF_CNT 2
81
82 #define TOUT_LOOP 100
83
84 #define PKT_MAXBUF_SIZE 1518
85 #define PKT_MINBUF_SIZE 64
86 #define PKT_MAXBLR_SIZE 1520
87
88 #ifdef __GNUC__
89 static char txbuf[DBUF_LENGTH] __aligned(8);
90 #else
91 #error txbuf must be aligned.
92 #endif
93
94 static uint rxIdx; /* index of the current RX buffer */
95 static uint txIdx; /* index of the current TX buffer */
96
97 /*
98 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
99 * immr->udata_bd address on Dual-Port RAM
100 * Provide for Double Buffering
101 */
102
103 struct common_buf_desc {
104 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
105 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
106 };
107
108 static struct common_buf_desc __iomem *rtx;
109
110 static int fec_send(struct eth_device *dev, void *packet, int length);
111 static int fec_recv(struct eth_device *dev);
112 static int fec_init(struct eth_device *dev, bd_t *bd);
113 static void fec_halt(struct eth_device *dev);
114 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
115 static void __mii_init(void);
116 #endif
117
fec_initialize(bd_t * bis)118 int fec_initialize(bd_t *bis)
119 {
120 struct eth_device *dev;
121 struct ether_fcc_info_s *efis;
122 int i;
123
124 for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
125 dev = malloc(sizeof(*dev));
126 if (dev == NULL)
127 hang();
128
129 memset(dev, 0, sizeof(*dev));
130
131 /* for FEC1 make sure that the name of the interface is the same
132 as the old one for compatibility reasons */
133 if (i == 0)
134 strcpy(dev->name, "FEC");
135 else
136 sprintf(dev->name, "FEC%d",
137 ether_fcc_info[i].ether_index + 1);
138
139 efis = ðer_fcc_info[i];
140
141 /*
142 * reset actual phy addr
143 */
144 efis->actual_phy_addr = -1;
145
146 dev->priv = efis;
147 dev->init = fec_init;
148 dev->halt = fec_halt;
149 dev->send = fec_send;
150 dev->recv = fec_recv;
151
152 eth_register(dev);
153
154 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
155 int retval;
156 struct mii_dev *mdiodev = mdio_alloc();
157 if (!mdiodev)
158 return -ENOMEM;
159 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
160 mdiodev->read = fec8xx_miiphy_read;
161 mdiodev->write = fec8xx_miiphy_write;
162
163 retval = mdio_register(mdiodev);
164 if (retval < 0)
165 return retval;
166 #endif
167 }
168 return 1;
169 }
170
fec_send(struct eth_device * dev,void * packet,int length)171 static int fec_send(struct eth_device *dev, void *packet, int length)
172 {
173 int j, rc;
174 struct ether_fcc_info_s *efis = dev->priv;
175 fec_t __iomem *fecp =
176 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
177
178 /* section 16.9.23.3
179 * Wait for ready
180 */
181 j = 0;
182 while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
183 (j < TOUT_LOOP)) {
184 udelay(1);
185 j++;
186 }
187 if (j >= TOUT_LOOP)
188 printf("TX not ready\n");
189
190 out_be32(&rtx->txbd[txIdx].cbd_bufaddr, (uint)packet);
191 out_be16(&rtx->txbd[txIdx].cbd_datlen, length);
192 setbits_be16(&rtx->txbd[txIdx].cbd_sc,
193 BD_ENET_TX_READY | BD_ENET_TX_LAST);
194
195 /* Activate transmit Buffer Descriptor polling */
196 /* Descriptor polling active */
197 out_be32(&fecp->fec_x_des_active, 0x01000000);
198
199 j = 0;
200 while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) &&
201 (j < TOUT_LOOP)) {
202 udelay(1);
203 j++;
204 }
205 if (j >= TOUT_LOOP)
206 printf("TX timeout\n");
207
208 /* return only status bits */;
209 rc = in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_STATS;
210
211 txIdx = (txIdx + 1) % TX_BUF_CNT;
212
213 return rc;
214 }
215
fec_recv(struct eth_device * dev)216 static int fec_recv(struct eth_device *dev)
217 {
218 struct ether_fcc_info_s *efis = dev->priv;
219 fec_t __iomem *fecp =
220 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
221 int length;
222
223 for (;;) {
224 /* section 16.9.23.2 */
225 if (in_be16(&rtx->rxbd[rxIdx].cbd_sc) & BD_ENET_RX_EMPTY) {
226 length = -1;
227 break; /* nothing received - leave for() loop */
228 }
229
230 length = in_be16(&rtx->rxbd[rxIdx].cbd_datlen);
231
232 if (!(in_be16(&rtx->rxbd[rxIdx].cbd_sc) & 0x003f)) {
233 uchar *rx = net_rx_packets[rxIdx];
234
235 length -= 4;
236
237 #if defined(CONFIG_CMD_CDP)
238 if ((rx[0] & 1) != 0 &&
239 memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 &&
240 !is_cdp_packet((uchar *)rx))
241 rx = NULL;
242 #endif
243 /*
244 * Pass the packet up to the protocol layers.
245 */
246 if (rx != NULL)
247 net_process_received_packet(rx, length);
248 }
249
250 /* Give the buffer back to the FEC. */
251 out_be16(&rtx->rxbd[rxIdx].cbd_datlen, 0);
252
253 /* wrap around buffer index when necessary */
254 if ((rxIdx + 1) >= PKTBUFSRX) {
255 out_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc,
256 BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
257 rxIdx = 0;
258 } else {
259 out_be16(&rtx->rxbd[rxIdx].cbd_sc, BD_ENET_RX_EMPTY);
260 rxIdx++;
261 }
262
263 /* Try to fill Buffer Descriptors */
264 /* Descriptor polling active */
265 out_be32(&fecp->fec_r_des_active, 0x01000000);
266 }
267
268 return length;
269 }
270
271 /**************************************************************
272 *
273 * FEC Ethernet Initialization Routine
274 *
275 *************************************************************/
276
277 #define FEC_ECNTRL_PINMUX 0x00000004
278 #define FEC_ECNTRL_ETHER_EN 0x00000002
279 #define FEC_ECNTRL_RESET 0x00000001
280
281 #define FEC_RCNTRL_BC_REJ 0x00000010
282 #define FEC_RCNTRL_PROM 0x00000008
283 #define FEC_RCNTRL_MII_MODE 0x00000004
284 #define FEC_RCNTRL_DRT 0x00000002
285 #define FEC_RCNTRL_LOOP 0x00000001
286
287 #define FEC_TCNTRL_FDEN 0x00000004
288 #define FEC_TCNTRL_HBC 0x00000002
289 #define FEC_TCNTRL_GTS 0x00000001
290
291 #define FEC_RESET_DELAY 50
292
293 #if defined(CONFIG_RMII)
294
fec_10Mbps(struct eth_device * dev)295 static inline void fec_10Mbps(struct eth_device *dev)
296 {
297 struct ether_fcc_info_s *efis = dev->priv;
298 int fecidx = efis->ether_index;
299 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
300 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
301
302 if ((unsigned int)fecidx >= 2)
303 hang();
304
305 setbits_be32(&immr->im_cpm.cp_cptr, mask);
306 }
307
fec_100Mbps(struct eth_device * dev)308 static inline void fec_100Mbps(struct eth_device *dev)
309 {
310 struct ether_fcc_info_s *efis = dev->priv;
311 int fecidx = efis->ether_index;
312 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
313 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
314
315 if ((unsigned int)fecidx >= 2)
316 hang();
317
318 clrbits_be32(&immr->im_cpm.cp_cptr, mask);
319 }
320
321 #endif
322
fec_full_duplex(struct eth_device * dev)323 static inline void fec_full_duplex(struct eth_device *dev)
324 {
325 struct ether_fcc_info_s *efis = dev->priv;
326 fec_t __iomem *fecp =
327 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
328
329 clrbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
330 setbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
331 }
332
fec_half_duplex(struct eth_device * dev)333 static inline void fec_half_duplex(struct eth_device *dev)
334 {
335 struct ether_fcc_info_s *efis = dev->priv;
336 fec_t __iomem *fecp =
337 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
338
339 setbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT);
340 clrbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
341 }
342
fec_pin_init(int fecidx)343 static void fec_pin_init(int fecidx)
344 {
345 bd_t *bd = gd->bd;
346 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
347
348 /*
349 * Set MII speed to 2.5 MHz or slightly below.
350 *
351 * According to the MPC860T (Rev. D) Fast ethernet controller user
352 * manual (6.2.14),
353 * the MII management interface clock must be less than or equal
354 * to 2.5 MHz.
355 * This MDC frequency is equal to system clock / (2 * MII_SPEED).
356 * Then MII_SPEED = system_clock / 2 * 2,5 MHz.
357 *
358 * All MII configuration is done via FEC1 registers:
359 */
360 out_be32(&immr->im_cpm.cp_fec1.fec_mii_speed,
361 ((bd->bi_intfreq + 4999999) / 5000000) << 1);
362
363 #if defined(CONFIG_MPC885) && defined(WANT_MII)
364 /* use MDC for MII */
365 setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080);
366 clrbits_be16(&immr->im_ioport.iop_pddir, 0x0080);
367 #endif
368
369 if (fecidx == 0) {
370 #if defined(CONFIG_ETHER_ON_FEC1)
371
372 #if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
373
374 #if !defined(CONFIG_RMII)
375
376 setbits_be16(&immr->im_ioport.iop_papar, 0xf830);
377 setbits_be16(&immr->im_ioport.iop_padir, 0x0830);
378 clrbits_be16(&immr->im_ioport.iop_padir, 0xf000);
379
380 setbits_be32(&immr->im_cpm.cp_pbpar, 0x00001001);
381 clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00001001);
382
383 setbits_be16(&immr->im_ioport.iop_pcpar, 0x000c);
384 clrbits_be16(&immr->im_ioport.iop_pcdir, 0x000c);
385
386 setbits_be32(&immr->im_cpm.cp_pepar, 0x00000003);
387 setbits_be32(&immr->im_cpm.cp_pedir, 0x00000003);
388 clrbits_be32(&immr->im_cpm.cp_peso, 0x00000003);
389
390 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
391
392 #else
393
394 #if !defined(CONFIG_FEC1_PHY_NORXERR)
395 setbits_be16(&immr->im_ioport.iop_papar, 0x1000);
396 clrbits_be16(&immr->im_ioport.iop_padir, 0x1000);
397 #endif
398 setbits_be16(&immr->im_ioport.iop_papar, 0xe810);
399 setbits_be16(&immr->im_ioport.iop_padir, 0x0810);
400 clrbits_be16(&immr->im_ioport.iop_padir, 0xe000);
401
402 setbits_be32(&immr->im_cpm.cp_pbpar, 0x00000001);
403 clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00000001);
404
405 setbits_be32(&immr->im_cpm.cp_cptr, 0x00000100);
406 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000050);
407
408 #endif /* !CONFIG_RMII */
409
410 #else
411 /*
412 * Configure all of port D for MII.
413 */
414 out_be16(&immr->im_ioport.iop_pdpar, 0x1fff);
415 out_be16(&immr->im_ioport.iop_pddir, 0x1fff);
416
417 #if defined(CONFIG_TARGET_MCR3000)
418 out_be16(&immr->im_ioport.iop_papar, 0xBBFF);
419 out_be16(&immr->im_ioport.iop_padir, 0x04F0);
420 out_be16(&immr->im_ioport.iop_paodr, 0x0000);
421
422 out_be32(&immr->im_cpm.cp_pbpar, 0x000133FF);
423 out_be32(&immr->im_cpm.cp_pbdir, 0x0003BF0F);
424 out_be16(&immr->im_cpm.cp_pbodr, 0x0000);
425
426 out_be16(&immr->im_ioport.iop_pcpar, 0x0400);
427 out_be16(&immr->im_ioport.iop_pcdir, 0x0080);
428 out_be16(&immr->im_ioport.iop_pcso , 0x0D53);
429 out_be16(&immr->im_ioport.iop_pcint, 0x0000);
430
431 out_be16(&immr->im_ioport.iop_pdpar, 0x03FE);
432 out_be16(&immr->im_ioport.iop_pddir, 0x1C09);
433
434 setbits_be32(&immr->im_ioport.utmode, 0x80);
435 #endif
436 #endif
437
438 #endif /* CONFIG_ETHER_ON_FEC1 */
439 } else if (fecidx == 1) {
440 #if defined(CONFIG_ETHER_ON_FEC2)
441
442 #if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
443
444 #if !defined(CONFIG_RMII)
445 setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc);
446 setbits_be32(&immr->im_cpm.cp_pedir, 0x0003fffc);
447 clrbits_be32(&immr->im_cpm.cp_peso, 0x000087fc);
448 setbits_be32(&immr->im_cpm.cp_peso, 0x00037800);
449
450 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
451 #else
452
453 #if !defined(CONFIG_FEC2_PHY_NORXERR)
454 setbits_be32(&immr->im_cpm.cp_pepar, 0x00000010);
455 setbits_be32(&immr->im_cpm.cp_pedir, 0x00000010);
456 clrbits_be32(&immr->im_cpm.cp_peso, 0x00000010);
457 #endif
458 setbits_be32(&immr->im_cpm.cp_pepar, 0x00039620);
459 setbits_be32(&immr->im_cpm.cp_pedir, 0x00039620);
460 setbits_be32(&immr->im_cpm.cp_peso, 0x00031000);
461 clrbits_be32(&immr->im_cpm.cp_peso, 0x00008620);
462
463 setbits_be32(&immr->im_cpm.cp_cptr, 0x00000080);
464 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000028);
465 #endif /* CONFIG_RMII */
466
467 #endif /* CONFIG_MPC885 */
468
469 #endif /* CONFIG_ETHER_ON_FEC2 */
470 }
471 }
472
fec_reset(fec_t __iomem * fecp)473 static int fec_reset(fec_t __iomem *fecp)
474 {
475 int i;
476
477 /* Whack a reset.
478 * A delay is required between a reset of the FEC block and
479 * initialization of other FEC registers because the reset takes
480 * some time to complete. If you don't delay, subsequent writes
481 * to FEC registers might get killed by the reset routine which is
482 * still in progress.
483 */
484
485 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
486 for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
487 (i < FEC_RESET_DELAY); ++i)
488 udelay(1);
489
490 if (i == FEC_RESET_DELAY)
491 return -1;
492
493 return 0;
494 }
495
fec_init(struct eth_device * dev,bd_t * bd)496 static int fec_init(struct eth_device *dev, bd_t *bd)
497 {
498 struct ether_fcc_info_s *efis = dev->priv;
499 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
500 fec_t __iomem *fecp =
501 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
502 int i;
503
504 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
505 /* the MII interface is connected to FEC1
506 * so for the miiphy_xxx function to work we must
507 * call mii_init since fec_halt messes the thing up
508 */
509 if (efis->ether_index != 0)
510 __mii_init();
511 #endif
512
513 if (fec_reset(fecp) < 0)
514 printf("FEC_RESET_DELAY timeout\n");
515
516 /* We use strictly polling mode only
517 */
518 out_be32(&fecp->fec_imask, 0);
519
520 /* Clear any pending interrupt
521 */
522 out_be32(&fecp->fec_ievent, 0xffc0);
523
524 /* No need to set the IVEC register */
525
526 /* Set station address
527 */
528 #define ea dev->enetaddr
529 out_be32(&fecp->fec_addr_low, (ea[0] << 24) | (ea[1] << 16) |
530 (ea[2] << 8) | ea[3]);
531 out_be16(&fecp->fec_addr_high, (ea[4] << 8) | ea[5]);
532 #undef ea
533
534 #if defined(CONFIG_CMD_CDP)
535 /*
536 * Turn on multicast address hash table
537 */
538 out_be32(&fecp->fec_hash_table_high, 0xffffffff);
539 out_be32(&fecp->fec_hash_table_low, 0xffffffff);
540 #else
541 /* Clear multicast address hash table
542 */
543 out_be32(&fecp->fec_hash_table_high, 0);
544 out_be32(&fecp->fec_hash_table_low, 0);
545 #endif
546
547 /* Set maximum receive buffer size.
548 */
549 out_be32(&fecp->fec_r_buff_size, PKT_MAXBLR_SIZE);
550
551 /* Set maximum frame length
552 */
553 out_be32(&fecp->fec_r_hash, PKT_MAXBUF_SIZE);
554
555 /*
556 * Setup Buffers and Buffer Descriptors
557 */
558 rxIdx = 0;
559 txIdx = 0;
560
561 if (!rtx)
562 rtx = (struct common_buf_desc __iomem *)
563 (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
564 /*
565 * Setup Receiver Buffer Descriptors (13.14.24.18)
566 * Settings:
567 * Empty, Wrap
568 */
569 for (i = 0; i < PKTBUFSRX; i++) {
570 out_be16(&rtx->rxbd[i].cbd_sc, BD_ENET_RX_EMPTY);
571 out_be16(&rtx->rxbd[i].cbd_datlen, 0); /* Reset */
572 out_be32(&rtx->rxbd[i].cbd_bufaddr, (uint)net_rx_packets[i]);
573 }
574 setbits_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc, BD_ENET_RX_WRAP);
575
576 /*
577 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
578 * Settings:
579 * Last, Tx CRC
580 */
581 for (i = 0; i < TX_BUF_CNT; i++) {
582 out_be16(&rtx->txbd[i].cbd_sc, BD_ENET_TX_LAST | BD_ENET_TX_TC);
583 out_be16(&rtx->txbd[i].cbd_datlen, 0); /* Reset */
584 out_be32(&rtx->txbd[i].cbd_bufaddr, (uint)txbuf);
585 }
586 setbits_be16(&rtx->txbd[TX_BUF_CNT - 1].cbd_sc, BD_ENET_TX_WRAP);
587
588 /* Set receive and transmit descriptor base
589 */
590 out_be32(&fecp->fec_r_des_start, (__force unsigned int)rtx->rxbd);
591 out_be32(&fecp->fec_x_des_start, (__force unsigned int)rtx->txbd);
592
593 /* Enable MII mode
594 */
595 /* Half duplex mode */
596 out_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT);
597 out_be32(&fecp->fec_x_cntrl, 0);
598
599 /* Enable big endian and don't care about SDMA FC.
600 */
601 out_be32(&fecp->fec_fun_code, 0x78000000);
602
603 /*
604 * Setup the pin configuration of the FEC
605 */
606 fec_pin_init(efis->ether_index);
607
608 rxIdx = 0;
609 txIdx = 0;
610
611 /*
612 * Now enable the transmit and receive processing
613 */
614 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
615
616 if (efis->phy_addr == -1) {
617 #ifdef CONFIG_SYS_DISCOVER_PHY
618 /*
619 * wait for the PHY to wake up after reset
620 */
621 efis->actual_phy_addr = mii_discover_phy(dev);
622
623 if (efis->actual_phy_addr == -1) {
624 printf("Unable to discover phy!\n");
625 return -1;
626 }
627 #else
628 efis->actual_phy_addr = -1;
629 #endif
630 } else {
631 efis->actual_phy_addr = efis->phy_addr;
632 }
633
634 #if defined(CONFIG_MII) && defined(CONFIG_RMII)
635 /*
636 * adapt the RMII speed to the speed of the phy
637 */
638 if (miiphy_speed(dev->name, efis->actual_phy_addr) == _100BASET)
639 fec_100Mbps(dev);
640 else
641 fec_10Mbps(dev);
642 #endif
643
644 #if defined(CONFIG_MII)
645 /*
646 * adapt to the half/full speed settings
647 */
648 if (miiphy_duplex(dev->name, efis->actual_phy_addr) == FULL)
649 fec_full_duplex(dev);
650 else
651 fec_half_duplex(dev);
652 #endif
653
654 /* And last, try to fill Rx Buffer Descriptors */
655 /* Descriptor polling active */
656 out_be32(&fecp->fec_r_des_active, 0x01000000);
657
658 efis->initialized = 1;
659
660 return 0;
661 }
662
663
fec_halt(struct eth_device * dev)664 static void fec_halt(struct eth_device *dev)
665 {
666 struct ether_fcc_info_s *efis = dev->priv;
667 fec_t __iomem *fecp =
668 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset);
669 int i;
670
671 /* avoid halt if initialized; mii gets stuck otherwise */
672 if (!efis->initialized)
673 return;
674
675 /* Whack a reset.
676 * A delay is required between a reset of the FEC block and
677 * initialization of other FEC registers because the reset takes
678 * some time to complete. If you don't delay, subsequent writes
679 * to FEC registers might get killed by the reset routine which is
680 * still in progress.
681 */
682
683 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
684 for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) &&
685 (i < FEC_RESET_DELAY); ++i)
686 udelay(1);
687
688 if (i == FEC_RESET_DELAY) {
689 printf("FEC_RESET_DELAY timeout\n");
690 return;
691 }
692
693 efis->initialized = 0;
694 }
695
696 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
697
698 /* Make MII read/write commands for the FEC.
699 */
700
701 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
702 (REG & 0x1f) << 18))
703
704 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
705 (REG & 0x1f) << 18) | \
706 (VAL & 0xffff))
707
708 /* Interrupt events/masks.
709 */
710 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
711 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
712 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
713 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
714 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
715 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
716 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
717 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
718 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
719 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
720
721 /* send command to phy using mii, wait for result */
722 static uint
mii_send(uint mii_cmd)723 mii_send(uint mii_cmd)
724 {
725 uint mii_reply;
726 fec_t __iomem *ep;
727 int cnt;
728 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
729
730 ep = &immr->im_cpm.cp_fec;
731
732 out_be32(&ep->fec_mii_data, mii_cmd); /* command to phy */
733
734 /* wait for mii complete */
735 cnt = 0;
736 while (!(in_be32(&ep->fec_ievent) & FEC_ENET_MII)) {
737 if (++cnt > 1000) {
738 printf("mii_send STUCK!\n");
739 break;
740 }
741 }
742 mii_reply = in_be32(&ep->fec_mii_data); /* result from phy */
743 out_be32(&ep->fec_ievent, FEC_ENET_MII); /* clear MII complete */
744 return mii_reply & 0xffff; /* data read from phy */
745 }
746 #endif
747
748 #if defined(CONFIG_SYS_DISCOVER_PHY)
mii_discover_phy(struct eth_device * dev)749 static int mii_discover_phy(struct eth_device *dev)
750 {
751 #define MAX_PHY_PASSES 11
752 uint phyno;
753 int pass;
754 uint phytype;
755 int phyaddr;
756
757 phyaddr = -1; /* didn't find a PHY yet */
758 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
759 if (pass > 1) {
760 /* PHY may need more time to recover from reset.
761 * The LXT970 needs 50ms typical, no maximum is
762 * specified, so wait 10ms before try again.
763 * With 11 passes this gives it 100ms to wake up.
764 */
765 udelay(10000); /* wait 10ms */
766 }
767 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
768 phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2));
769 if (phytype != 0xffff) {
770 phyaddr = phyno;
771 phytype |= mii_send(mk_mii_read(phyno,
772 MII_PHYSID1)) << 16;
773 }
774 }
775 }
776 if (phyaddr < 0)
777 printf("No PHY device found.\n");
778
779 return phyaddr;
780 }
781 #endif /* CONFIG_SYS_DISCOVER_PHY */
782
783 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
784
785 /****************************************************************************
786 * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet
787 * This function is a subset of eth_init
788 ****************************************************************************
789 */
__mii_init(void)790 static void __mii_init(void)
791 {
792 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
793 fec_t __iomem *fecp = &immr->im_cpm.cp_fec;
794
795 if (fec_reset(fecp) < 0)
796 printf("FEC_RESET_DELAY timeout\n");
797
798 /* We use strictly polling mode only
799 */
800 out_be32(&fecp->fec_imask, 0);
801
802 /* Clear any pending interrupt
803 */
804 out_be32(&fecp->fec_ievent, 0xffc0);
805
806 /* Now enable the transmit and receive processing
807 */
808 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
809 }
810
mii_init(void)811 void mii_init(void)
812 {
813 int i;
814
815 __mii_init();
816
817 /* Setup the pin configuration of the FEC(s)
818 */
819 for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
820 fec_pin_init(ether_fcc_info[i].ether_index);
821 }
822
823 /*****************************************************************************
824 * Read and write a MII PHY register, routines used by MII Utilities
825 *
826 * FIXME: These routines are expected to return 0 on success, but mii_send
827 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
828 * no PHY connected...
829 * For now always return 0.
830 * FIXME: These routines only work after calling eth_init() at least once!
831 * Otherwise they hang in mii_send() !!! Sorry!
832 *****************************************************************************/
833
fec8xx_miiphy_read(struct mii_dev * bus,int addr,int devad,int reg)834 int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
835 {
836 unsigned short value = 0;
837 short rdreg; /* register working value */
838
839 rdreg = mii_send(mk_mii_read(addr, reg));
840
841 value = rdreg;
842 return value;
843 }
844
fec8xx_miiphy_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)845 int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
846 u16 value)
847 {
848 (void)mii_send(mk_mii_write(addr, reg, value));
849
850 return 0;
851 }
852 #endif
853