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1 /*
2  * Copyright © 2008 Keith Packard
3  *
4  * Permission to use, copy, modify, distribute, and sell this software and its
5  * documentation for any purpose is hereby granted without fee, provided that
6  * the above copyright notice appear in all copies and that both that copyright
7  * notice and this permission notice appear in supporting documentation, and
8  * that the name of the copyright holders not be used in advertising or
9  * publicity pertaining to distribution of the software without specific,
10  * written prior permission.  The copyright holders make no representations
11  * about the suitability of this software for any purpose.  It is provided "as
12  * is" without express or implied warranty.
13  *
14  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20  * OF THIS SOFTWARE.
21  */
22 
23 #ifndef _DRM_DP_HELPER_H_
24 #define _DRM_DP_HELPER_H_
25 
26 /*
27  * Unless otherwise noted, all values are from the DP 1.1a spec.  Note that
28  * DP and DPCD versions are independent.  Differences from 1.0 are not noted,
29  * 1.0 devices basically don't exist in the wild.
30  *
31  * Abbreviations, in chronological order:
32  *
33  * eDP: Embedded DisplayPort version 1
34  * DPI: DisplayPort Interoperability Guideline v1.1a
35  * 1.2: DisplayPort 1.2
36  * MST: Multistream Transport - part of DP 1.2a
37  *
38  * 1.2 formally includes both eDP and DPI definitions.
39  */
40 
41 #define DP_AUX_I2C_WRITE		0x0
42 #define DP_AUX_I2C_READ			0x1
43 #define DP_AUX_I2C_STATUS		0x2
44 #define DP_AUX_I2C_MOT			0x4
45 #define DP_AUX_NATIVE_WRITE		0x8
46 #define DP_AUX_NATIVE_READ		0x9
47 
48 #define DP_AUX_NATIVE_REPLY_ACK		(0x0 << 0)
49 #define DP_AUX_NATIVE_REPLY_NACK	(0x1 << 0)
50 #define DP_AUX_NATIVE_REPLY_DEFER	(0x2 << 0)
51 #define DP_AUX_NATIVE_REPLY_MASK	(0x3 << 0)
52 
53 #define DP_AUX_I2C_REPLY_ACK		(0x0 << 2)
54 #define DP_AUX_I2C_REPLY_NACK		(0x1 << 2)
55 #define DP_AUX_I2C_REPLY_DEFER		(0x2 << 2)
56 #define DP_AUX_I2C_REPLY_MASK		(0x3 << 2)
57 
58 /* AUX CH addresses */
59 /* DPCD */
60 #define DP_DPCD_REV                         0x000
61 
62 #define DP_MAX_LINK_RATE                    0x001
63 
64 #define DP_MAX_LANE_COUNT                   0x002
65 # define DP_MAX_LANE_COUNT_MASK		    0x1f
66 # define DP_TPS3_SUPPORTED		    (1 << 6) /* 1.2 */
67 # define DP_ENHANCED_FRAME_CAP		    (1 << 7)
68 
69 #define DP_MAX_DOWNSPREAD                   0x003
70 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING  (1 << 6)
71 
72 #define DP_NORP                             0x004
73 
74 #define DP_DOWNSTREAMPORT_PRESENT           0x005
75 # define DP_DWN_STRM_PORT_PRESENT           (1 << 0)
76 # define DP_DWN_STRM_PORT_TYPE_MASK         0x06
77 # define DP_DWN_STRM_PORT_TYPE_DP           (0 << 1)
78 # define DP_DWN_STRM_PORT_TYPE_ANALOG       (1 << 1)
79 # define DP_DWN_STRM_PORT_TYPE_TMDS         (2 << 1)
80 # define DP_DWN_STRM_PORT_TYPE_OTHER        (3 << 1)
81 # define DP_FORMAT_CONVERSION               (1 << 3)
82 # define DP_DETAILED_CAP_INFO_AVAILABLE	    (1 << 4) /* DPI */
83 
84 #define DP_MAIN_LINK_CHANNEL_CODING         0x006
85 
86 #define DP_DOWN_STREAM_PORT_COUNT	    0x007
87 # define DP_PORT_COUNT_MASK		    0x0f
88 # define DP_MSA_TIMING_PAR_IGNORED	    (1 << 6) /* eDP */
89 # define DP_OUI_SUPPORT			    (1 << 7)
90 
91 #define DP_I2C_SPEED_CAP		    0x00c    /* DPI */
92 # define DP_I2C_SPEED_1K		    0x01
93 # define DP_I2C_SPEED_5K		    0x02
94 # define DP_I2C_SPEED_10K		    0x04
95 # define DP_I2C_SPEED_100K		    0x08
96 # define DP_I2C_SPEED_400K		    0x10
97 # define DP_I2C_SPEED_1M		    0x20
98 
99 #define DP_EDP_CONFIGURATION_CAP            0x00d   /* XXX 1.2? */
100 #define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
101 
102 /* Multiple stream transport */
103 #define DP_FAUX_CAP			    0x020   /* 1.2 */
104 # define DP_FAUX_CAP_1			    (1 << 0)
105 
106 #define DP_MSTM_CAP			    0x021   /* 1.2 */
107 # define DP_MST_CAP			    (1 << 0)
108 
109 #define DP_GUID				    0x030   /* 1.2 */
110 
111 #define DP_PSR_SUPPORT                      0x070   /* XXX 1.2? */
112 # define DP_PSR_IS_SUPPORTED                1
113 #define DP_PSR_CAPS                         0x071   /* XXX 1.2? */
114 # define DP_PSR_NO_TRAIN_ON_EXIT            1
115 # define DP_PSR_SETUP_TIME_330              (0 << 1)
116 # define DP_PSR_SETUP_TIME_275              (1 << 1)
117 # define DP_PSR_SETUP_TIME_220              (2 << 1)
118 # define DP_PSR_SETUP_TIME_165              (3 << 1)
119 # define DP_PSR_SETUP_TIME_110              (4 << 1)
120 # define DP_PSR_SETUP_TIME_55               (5 << 1)
121 # define DP_PSR_SETUP_TIME_0                (6 << 1)
122 # define DP_PSR_SETUP_TIME_MASK             (7 << 1)
123 # define DP_PSR_SETUP_TIME_SHIFT            1
124 
125 /*
126  * 0x80-0x8f describe downstream port capabilities, but there are two layouts
127  * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set.  If it was not,
128  * each port's descriptor is one byte wide.  If it was set, each port's is
129  * four bytes wide, starting with the one byte from the base info.  As of
130  * DP interop v1.1a only VGA defines additional detail.
131  */
132 
133 /* offset 0 */
134 #define DP_DOWNSTREAM_PORT_0		    0x80
135 # define DP_DS_PORT_TYPE_MASK		    (7 << 0)
136 # define DP_DS_PORT_TYPE_DP		    0
137 # define DP_DS_PORT_TYPE_VGA		    1
138 # define DP_DS_PORT_TYPE_DVI		    2
139 # define DP_DS_PORT_TYPE_HDMI		    3
140 # define DP_DS_PORT_TYPE_NON_EDID	    4
141 # define DP_DS_PORT_HPD			    (1 << 3)
142 /* offset 1 for VGA is maximum megapixels per second / 8 */
143 /* offset 2 */
144 # define DP_DS_VGA_MAX_BPC_MASK		    (3 << 0)
145 # define DP_DS_VGA_8BPC			    0
146 # define DP_DS_VGA_10BPC		    1
147 # define DP_DS_VGA_12BPC		    2
148 # define DP_DS_VGA_16BPC		    3
149 
150 /* link configuration */
151 #define	DP_LINK_BW_SET		            0x100
152 # define DP_LINK_BW_1_62		    0x06
153 # define DP_LINK_BW_2_7			    0x0a
154 # define DP_LINK_BW_5_4			    0x14    /* 1.2 */
155 
156 #define DP_LANE_COUNT_SET	            0x101
157 # define DP_LANE_COUNT_MASK		    0x0f
158 # define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
159 
160 #define DP_TRAINING_PATTERN_SET	            0x102
161 # define DP_TRAINING_PATTERN_DISABLE	    0
162 # define DP_TRAINING_PATTERN_1		    1
163 # define DP_TRAINING_PATTERN_2		    2
164 # define DP_TRAINING_PATTERN_3		    3	    /* 1.2 */
165 # define DP_TRAINING_PATTERN_MASK	    0x3
166 
167 # define DP_LINK_QUAL_PATTERN_DISABLE	    (0 << 2)
168 # define DP_LINK_QUAL_PATTERN_D10_2	    (1 << 2)
169 # define DP_LINK_QUAL_PATTERN_ERROR_RATE    (2 << 2)
170 # define DP_LINK_QUAL_PATTERN_PRBS7	    (3 << 2)
171 # define DP_LINK_QUAL_PATTERN_MASK	    (3 << 2)
172 
173 # define DP_RECOVERED_CLOCK_OUT_EN	    (1 << 4)
174 # define DP_LINK_SCRAMBLING_DISABLE	    (1 << 5)
175 
176 # define DP_SYMBOL_ERROR_COUNT_BOTH	    (0 << 6)
177 # define DP_SYMBOL_ERROR_COUNT_DISPARITY    (1 << 6)
178 # define DP_SYMBOL_ERROR_COUNT_SYMBOL	    (2 << 6)
179 # define DP_SYMBOL_ERROR_COUNT_MASK	    (3 << 6)
180 
181 #define DP_TRAINING_LANE0_SET		    0x103
182 #define DP_TRAINING_LANE1_SET		    0x104
183 #define DP_TRAINING_LANE2_SET		    0x105
184 #define DP_TRAINING_LANE3_SET		    0x106
185 
186 # define DP_TRAIN_VOLTAGE_SWING_MASK	    0x3
187 # define DP_TRAIN_VOLTAGE_SWING_SHIFT	    0
188 # define DP_TRAIN_MAX_SWING_REACHED	    (1 << 2)
189 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
190 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
191 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
192 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
193 
194 # define DP_TRAIN_PRE_EMPHASIS_MASK	    (3 << 3)
195 # define DP_TRAIN_PRE_EMPH_LEVEL_0		(0 << 3)
196 # define DP_TRAIN_PRE_EMPH_LEVEL_1		(1 << 3)
197 # define DP_TRAIN_PRE_EMPH_LEVEL_2		(2 << 3)
198 # define DP_TRAIN_PRE_EMPH_LEVEL_3		(3 << 3)
199 
200 # define DP_TRAIN_PRE_EMPHASIS_SHIFT	    3
201 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)
202 
203 #define DP_DOWNSPREAD_CTRL		    0x107
204 # define DP_SPREAD_AMP_0_5		    (1 << 4)
205 # define DP_MSA_TIMING_PAR_IGNORE_EN	    (1 << 7) /* eDP */
206 
207 #define DP_MAIN_LINK_CHANNEL_CODING_SET	    0x108
208 # define DP_SET_ANSI_8B10B		    (1 << 0)
209 
210 #define DP_I2C_SPEED_CONTROL_STATUS	    0x109   /* DPI */
211 /* bitmask as for DP_I2C_SPEED_CAP */
212 
213 #define DP_EDP_CONFIGURATION_SET            0x10a   /* XXX 1.2? */
214 
215 #define DP_MSTM_CTRL			    0x111   /* 1.2 */
216 # define DP_MST_EN			    (1 << 0)
217 # define DP_UP_REQ_EN			    (1 << 1)
218 # define DP_UPSTREAM_IS_SRC		    (1 << 2)
219 
220 #define DP_PSR_EN_CFG			    0x170   /* XXX 1.2? */
221 # define DP_PSR_ENABLE			    (1 << 0)
222 # define DP_PSR_MAIN_LINK_ACTIVE	    (1 << 1)
223 # define DP_PSR_CRC_VERIFICATION	    (1 << 2)
224 # define DP_PSR_FRAME_CAPTURE		    (1 << 3)
225 
226 #define DP_ADAPTER_CTRL			    0x1a0
227 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE   (1 << 0)
228 
229 #define DP_BRANCH_DEVICE_CTRL		    0x1a1
230 # define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
231 
232 #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
233 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
234 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
235 
236 #define DP_SINK_COUNT			    0x200
237 /* prior to 1.2 bit 7 was reserved mbz */
238 # define DP_GET_SINK_COUNT(x)		    ((((x) & 0x80) >> 1) | ((x) & 0x3f))
239 # define DP_SINK_CP_READY		    (1 << 6)
240 
241 #define DP_DEVICE_SERVICE_IRQ_VECTOR	    0x201
242 # define DP_REMOTE_CONTROL_COMMAND_PENDING  (1 << 0)
243 # define DP_AUTOMATED_TEST_REQUEST	    (1 << 1)
244 # define DP_CP_IRQ			    (1 << 2)
245 # define DP_MCCS_IRQ			    (1 << 3)
246 # define DP_DOWN_REP_MSG_RDY		    (1 << 4) /* 1.2 MST */
247 # define DP_UP_REQ_MSG_RDY		    (1 << 5) /* 1.2 MST */
248 # define DP_SINK_SPECIFIC_IRQ		    (1 << 6)
249 
250 #define DP_LANE0_1_STATUS		    0x202
251 #define DP_LANE2_3_STATUS		    0x203
252 # define DP_LANE_CR_DONE		    (1 << 0)
253 # define DP_LANE_CHANNEL_EQ_DONE	    (1 << 1)
254 # define DP_LANE_SYMBOL_LOCKED		    (1 << 2)
255 
256 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE |		\
257 			    DP_LANE_CHANNEL_EQ_DONE |	\
258 			    DP_LANE_SYMBOL_LOCKED)
259 
260 #define DP_LANE_ALIGN_STATUS_UPDATED	    0x204
261 
262 #define DP_INTERLANE_ALIGN_DONE		    (1 << 0)
263 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED   (1 << 6)
264 #define DP_LINK_STATUS_UPDATED		    (1 << 7)
265 
266 #define DP_SINK_STATUS			    0x205
267 #define DP_SINK_STATUS_PORT0_IN_SYNC	    (1 << 0)
268 
269 #define DP_RECEIVE_PORT_0_STATUS	    (1 << 0)
270 #define DP_RECEIVE_PORT_1_STATUS	    (1 << 1)
271 
272 #define DP_ADJUST_REQUEST_LANE0_1	    0x206
273 #define DP_ADJUST_REQUEST_LANE2_3	    0x207
274 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK  0x03
275 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
276 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK   0x0c
277 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT  2
278 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK  0x30
279 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
280 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK   0xc0
281 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT  6
282 
283 #define DP_TEST_REQUEST			    0x218
284 # define DP_TEST_LINK_TRAINING		    (1 << 0)
285 # define DP_TEST_LINK_VIDEO_PATTERN	    (1 << 1)
286 # define DP_TEST_LINK_EDID_READ		    (1 << 2)
287 # define DP_TEST_LINK_PHY_TEST_PATTERN	    (1 << 3) /* DPCD >= 1.1 */
288 # define DP_TEST_LINK_FAUX_PATTERN	    (1 << 4) /* DPCD >= 1.2 */
289 
290 #define DP_TEST_LINK_RATE		    0x219
291 # define DP_LINK_RATE_162		    (0x6)
292 # define DP_LINK_RATE_27		    (0xa)
293 
294 #define DP_TEST_LANE_COUNT		    0x220
295 
296 #define DP_TEST_PATTERN			    0x221
297 
298 #define DP_TEST_CRC_R_CR		    0x240
299 #define DP_TEST_CRC_G_Y			    0x242
300 #define DP_TEST_CRC_B_CB		    0x244
301 
302 #define DP_TEST_SINK_MISC		    0x246
303 #define DP_TEST_CRC_SUPPORTED		    (1 << 5)
304 
305 #define DP_TEST_RESPONSE		    0x260
306 # define DP_TEST_ACK			    (1 << 0)
307 # define DP_TEST_NAK			    (1 << 1)
308 # define DP_TEST_EDID_CHECKSUM_WRITE	    (1 << 2)
309 
310 #define DP_TEST_EDID_CHECKSUM		    0x261
311 
312 #define DP_TEST_SINK			    0x270
313 #define DP_TEST_SINK_START	    (1 << 0)
314 
315 #define DP_PAYLOAD_TABLE_UPDATE_STATUS      0x2c0   /* 1.2 MST */
316 # define DP_PAYLOAD_TABLE_UPDATED           (1 << 0)
317 # define DP_PAYLOAD_ACT_HANDLED             (1 << 1)
318 
319 #define DP_VC_PAYLOAD_ID_SLOT_1             0x2c1   /* 1.2 MST */
320 /* up to ID_SLOT_63 at 0x2ff */
321 
322 #define DP_SOURCE_OUI			    0x300
323 #define DP_SINK_OUI			    0x400
324 #define DP_BRANCH_OUI			    0x500
325 
326 #define DP_SET_POWER                        0x600
327 # define DP_SET_POWER_D0                    0x1
328 # define DP_SET_POWER_D3                    0x2
329 # define DP_SET_POWER_MASK                  0x3
330 
331 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE	    0x1000   /* 1.2 MST */
332 #define DP_SIDEBAND_MSG_UP_REP_BASE	    0x1200   /* 1.2 MST */
333 #define DP_SIDEBAND_MSG_DOWN_REP_BASE	    0x1400   /* 1.2 MST */
334 #define DP_SIDEBAND_MSG_UP_REQ_BASE	    0x1600   /* 1.2 MST */
335 
336 #define DP_SINK_COUNT_ESI		    0x2002   /* 1.2 */
337 /* 0-5 sink count */
338 # define DP_SINK_COUNT_CP_READY             (1 << 6)
339 
340 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0   0x2003   /* 1.2 */
341 
342 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1   0x2004   /* 1.2 */
343 
344 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0     0x2005   /* 1.2 */
345 
346 #define DP_PSR_ERROR_STATUS                 0x2006  /* XXX 1.2? */
347 # define DP_PSR_LINK_CRC_ERROR              (1 << 0)
348 # define DP_PSR_RFB_STORAGE_ERROR           (1 << 1)
349 
350 #define DP_PSR_ESI                          0x2007  /* XXX 1.2? */
351 # define DP_PSR_CAPS_CHANGE                 (1 << 0)
352 
353 #define DP_PSR_STATUS                       0x2008  /* XXX 1.2? */
354 # define DP_PSR_SINK_INACTIVE               0
355 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED      1
356 # define DP_PSR_SINK_ACTIVE_RFB             2
357 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED     3
358 # define DP_PSR_SINK_ACTIVE_RESYNC          4
359 # define DP_PSR_SINK_INTERNAL_ERROR         7
360 # define DP_PSR_SINK_STATE_MASK             0x07
361 
362 /* DP 1.2 Sideband message defines */
363 /* peer device type - DP 1.2a Table 2-92 */
364 #define DP_PEER_DEVICE_NONE		0x0
365 #define DP_PEER_DEVICE_SOURCE_OR_SST	0x1
366 #define DP_PEER_DEVICE_MST_BRANCHING	0x2
367 #define DP_PEER_DEVICE_SST_SINK		0x3
368 #define DP_PEER_DEVICE_DP_LEGACY_CONV	0x4
369 
370 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
371 #define DP_LINK_ADDRESS			0x01
372 #define DP_CONNECTION_STATUS_NOTIFY	0x02
373 #define DP_ENUM_PATH_RESOURCES		0x10
374 #define DP_ALLOCATE_PAYLOAD		0x11
375 #define DP_QUERY_PAYLOAD		0x12
376 #define DP_RESOURCE_STATUS_NOTIFY	0x13
377 #define DP_CLEAR_PAYLOAD_ID_TABLE	0x14
378 #define DP_REMOTE_DPCD_READ		0x20
379 #define DP_REMOTE_DPCD_WRITE		0x21
380 #define DP_REMOTE_I2C_READ		0x22
381 #define DP_REMOTE_I2C_WRITE		0x23
382 #define DP_POWER_UP_PHY			0x24
383 #define DP_POWER_DOWN_PHY		0x25
384 #define DP_SINK_EVENT_NOTIFY		0x30
385 #define DP_QUERY_STREAM_ENC_STATUS	0x38
386 
387 /* DP 1.2 MST sideband nak reasons - table 2.84 */
388 #define DP_NAK_WRITE_FAILURE		0x01
389 #define DP_NAK_INVALID_READ		0x02
390 #define DP_NAK_CRC_FAILURE		0x03
391 #define DP_NAK_BAD_PARAM		0x04
392 #define DP_NAK_DEFER			0x05
393 #define DP_NAK_LINK_FAILURE		0x06
394 #define DP_NAK_NO_RESOURCES		0x07
395 #define DP_NAK_DPCD_FAIL		0x08
396 #define DP_NAK_I2C_NAK			0x09
397 #define DP_NAK_ALLOCATE_FAIL		0x0a
398 
399 #define MODE_I2C_START	1
400 #define MODE_I2C_WRITE	2
401 #define MODE_I2C_READ	4
402 #define MODE_I2C_STOP	8
403 
404 /* Rest of file omitted as it is not used in U-Boot */
405 
406 #endif /* _DRM_DP_HELPER_H_ */
407