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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2009
4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5  */
6 
7 #ifndef __DW_UDC_H
8 #define __DW_UDC_H
9 
10 /*
11  * Defines for  USBD
12  *
13  * The udc_ahb controller has three AHB slaves:
14  *
15  * 1.  THe UDC registers
16  * 2.  The plug detect
17  * 3.  The RX/TX FIFO
18  */
19 
20 #define MAX_ENDPOINTS		16
21 
22 struct udc_endp_regs {
23 	u32 endp_cntl;
24 	u32 endp_status;
25 	u32 endp_bsorfn;
26 	u32 endp_maxpacksize;
27 	u32 reserved_1;
28 	u32 endp_desc_point;
29 	u32 reserved_2;
30 	u32 write_done;
31 };
32 
33 /* Endpoint Control Register definitions */
34 
35 #define  ENDP_CNTL_STALL		0x00000001
36 #define  ENDP_CNTL_FLUSH		0x00000002
37 #define  ENDP_CNTL_SNOOP		0x00000004
38 #define  ENDP_CNTL_POLL			0x00000008
39 #define  ENDP_CNTL_CONTROL		0x00000000
40 #define  ENDP_CNTL_ISO			0x00000010
41 #define  ENDP_CNTL_BULK			0x00000020
42 #define  ENDP_CNTL_INT			0x00000030
43 #define  ENDP_CNTL_NAK			0x00000040
44 #define  ENDP_CNTL_SNAK			0x00000080
45 #define  ENDP_CNTL_CNAK			0x00000100
46 #define  ENDP_CNTL_RRDY			0x00000200
47 
48 /* Endpoint Satus Register definitions */
49 
50 #define  ENDP_STATUS_PIDMSK		0x0000000f
51 #define  ENDP_STATUS_OUTMSK		0x00000030
52 #define  ENDP_STATUS_OUT_NONE		0x00000000
53 #define  ENDP_STATUS_OUT_DATA		0x00000010
54 #define  ENDP_STATUS_OUT_SETUP		0x00000020
55 #define  ENDP_STATUS_IN			0x00000040
56 #define  ENDP_STATUS_BUFFNAV		0x00000080
57 #define  ENDP_STATUS_FATERR		0x00000100
58 #define  ENDP_STATUS_HOSTBUSERR		0x00000200
59 #define  ENDP_STATUS_TDC		0x00000400
60 #define  ENDP_STATUS_RXPKTMSK		0x003ff800
61 
62 struct udc_regs {
63 	struct udc_endp_regs in_regs[MAX_ENDPOINTS];
64 	struct udc_endp_regs out_regs[MAX_ENDPOINTS];
65 	u32 dev_conf;
66 	u32 dev_cntl;
67 	u32 dev_stat;
68 	u32 dev_int;
69 	u32 dev_int_mask;
70 	u32 endp_int;
71 	u32 endp_int_mask;
72 	u32 reserved_3[0x39];
73 	u32 reserved_4;		/* offset 0x500 */
74 	u32 udc_endp_reg[MAX_ENDPOINTS];
75 };
76 
77 /* Device Configuration Register definitions */
78 
79 #define  DEV_CONF_HS_SPEED		0x00000000
80 #define  DEV_CONF_LS_SPEED		0x00000002
81 #define  DEV_CONF_FS_SPEED		0x00000003
82 #define  DEV_CONF_REMWAKEUP		0x00000004
83 #define  DEV_CONF_SELFPOW		0x00000008
84 #define  DEV_CONF_SYNCFRAME		0x00000010
85 #define  DEV_CONF_PHYINT_8		0x00000020
86 #define  DEV_CONF_PHYINT_16		0x00000000
87 #define  DEV_CONF_UTMI_BIDIR		0x00000040
88 #define  DEV_CONF_STATUS_STALL		0x00000080
89 
90 /* Device Control Register definitions */
91 
92 #define  DEV_CNTL_RESUME		0x00000001
93 #define  DEV_CNTL_TFFLUSH		0x00000002
94 #define  DEV_CNTL_RXDMAEN		0x00000004
95 #define  DEV_CNTL_TXDMAEN		0x00000008
96 #define  DEV_CNTL_DESCRUPD		0x00000010
97 #define  DEV_CNTL_BIGEND		0x00000020
98 #define  DEV_CNTL_BUFFILL		0x00000040
99 #define  DEV_CNTL_TSHLDEN		0x00000080
100 #define  DEV_CNTL_BURSTEN		0x00000100
101 #define  DEV_CNTL_DMAMODE		0x00000200
102 #define  DEV_CNTL_SOFTDISCONNECT	0x00000400
103 #define  DEV_CNTL_SCALEDOWN		0x00000800
104 #define  DEV_CNTL_BURSTLENU		0x00010000
105 #define  DEV_CNTL_BURSTLENMSK		0x00ff0000
106 #define  DEV_CNTL_TSHLDLENU		0x01000000
107 #define  DEV_CNTL_TSHLDLENMSK		0xff000000
108 
109 /* Device Status Register definitions */
110 
111 #define  DEV_STAT_CFG			0x0000000f
112 #define  DEV_STAT_INTF			0x000000f0
113 #define  DEV_STAT_ALT			0x00000f00
114 #define  DEV_STAT_SUSP			0x00001000
115 #define  DEV_STAT_ENUM			0x00006000
116 #define  DEV_STAT_ENUM_SPEED_HS		0x00000000
117 #define  DEV_STAT_ENUM_SPEED_FS		0x00002000
118 #define  DEV_STAT_ENUM_SPEED_LS		0x00004000
119 #define  DEV_STAT_RXFIFO_EMPTY		0x00008000
120 #define  DEV_STAT_PHY_ERR		0x00010000
121 #define  DEV_STAT_TS			0xf0000000
122 
123 /* Device Interrupt Register definitions */
124 
125 #define  DEV_INT_MSK			0x0000007f
126 #define  DEV_INT_SETCFG			0x00000001
127 #define  DEV_INT_SETINTF		0x00000002
128 #define  DEV_INT_INACTIVE		0x00000004
129 #define  DEV_INT_USBRESET		0x00000008
130 #define  DEV_INT_SUSPUSB		0x00000010
131 #define  DEV_INT_SOF			0x00000020
132 #define  DEV_INT_ENUM			0x00000040
133 
134 /* Endpoint Interrupt Register definitions */
135 
136 #define  ENDP0_INT_CTRLIN		0x00000001
137 #define  ENDP1_INT_BULKIN		0x00000002
138 #define  ENDP_INT_NONISOIN_MSK		0x0000AAAA
139 #define  ENDP2_INT_BULKIN		0x00000004
140 #define  ENDP0_INT_CTRLOUT		0x00010000
141 #define  ENDP1_INT_BULKOUT		0x00020000
142 #define  ENDP2_INT_BULKOUT		0x00040000
143 #define  ENDP_INT_NONISOOUT_MSK		0x55540000
144 
145 /* Endpoint Register definitions */
146 #define  ENDP_EPDIR_OUT			0x00000000
147 #define  ENDP_EPDIR_IN			0x00000010
148 #define  ENDP_EPTYPE_CNTL		0x0
149 #define  ENDP_EPTYPE_ISO		0x1
150 #define  ENDP_EPTYPE_BULK		0x2
151 #define  ENDP_EPTYPE_INT		0x3
152 
153 /*
154  * Defines for Plug Detect
155  */
156 
157 struct plug_regs {
158 	u32 plug_state;
159 	u32 plug_pending;
160 };
161 
162 /* Plug State Register definitions */
163 #define  PLUG_STATUS_EN			0x1
164 #define  PLUG_STATUS_ATTACHED		0x2
165 #define  PLUG_STATUS_PHY_RESET		0x4
166 #define  PLUG_STATUS_PHY_MODE		0x8
167 
168 /*
169  * Defines for UDC FIFO (Slave Mode)
170  */
171 struct udcfifo_regs {
172 	u32 *fifo_p;
173 };
174 
175 /*
176  * UDC endpoint definitions
177  */
178 #define  UDC_EP0			0
179 #define  UDC_EP1			1
180 #define  UDC_EP2			2
181 #define  UDC_EP3			3
182 
183 #endif /* __DW_UDC_H */
184