Lines Matching refs:reset

16 provides greater implementation details around the reset code, specifically
19 General reset code flow
22 The ARM Trusted Firmware (TF) reset code is implemented in BL1 by default. The
25 |Default reset code flow|
27 This diagram shows the default, unoptimised reset flow. Depending on the system
34 this case. Please refer to section 6 "Using BL31 entrypoint as the reset
37 Programmable CPU reset address
40 By default, the TF assumes that the CPU reset address is not programmable.
42 they reset. Further logic is then required to identify whether it is a cold or
45 If the reset vector address (reflected in the reset vector base address register
47 at the right address, both on a cold and warm reset. Therefore, the boot type
50 |Reset code flow with programmable reset address|
53 This option only affects the TF reset image, which is BL1 by default or BL31 if
56 On both the FVP and Juno platforms, the reset vector address is not programmable
62 By default, the TF assumes that several CPUs may be released out of reset.
72 |Reset code flow with single CPU released out of reset|
75 option only affects the TF reset image, which is BL1 by default or BL31 if
80 reset. Therefore, both platform ports use ``COLD_BOOT_SINGLE_CPU=0``.
82 Programmable CPU reset address, Cold boot on a single CPU
86 a programmable CPU reset address and which release a single CPU out of reset.
90 |Reset code flow with programmable reset address and single CPU released out of reset|
93 and ``PROGRAMMABLE_RESET_ADDRESS=1``. These options only affect the TF reset
96 Using BL31 entrypoint as the reset address
103 to always reset to BL31 which eliminates the need for BL1 and BL2.
110 reset vector base address, before the application processor is powered on.
115 Although the ARM FVP platform does not support programming the reset base
120 SRAM and all CPU reset vectors be changed from the default ``0x0`` to this run
123 Although technically it would be possible to program the reset base address with
133 In this configuration, BL31 uses the same reset framework and code as the one
138 In the default, unoptimised BL31 reset flow, on a warm boot a CPU is directed
163 .. |Default reset code flow| image:: diagrams/default_reset_code.png?raw=true
164 .. |Reset code flow with programmable reset address| image:: diagrams/reset_code_no_boot_type_check…
165 .. |Reset code flow with single CPU released out of reset| image:: diagrams/reset_code_no_cpu_check…
166 .. |Reset code flow with programmable reset address and single CPU released out of reset| image:: d…