Lines Matching refs:U
15 #define MIDR_IMPL_MASK U(0xff)
16 #define MIDR_IMPL_SHIFT U(0x18)
17 #define MIDR_VAR_SHIFT U(20)
18 #define MIDR_VAR_BITS U(4)
19 #define MIDR_VAR_MASK U(0xf)
20 #define MIDR_REV_SHIFT U(0)
21 #define MIDR_REV_BITS U(4)
22 #define MIDR_REV_MASK U(0xf)
23 #define MIDR_PN_MASK U(0xfff)
24 #define MIDR_PN_SHIFT U(0x4)
29 #define MPIDR_MT_MASK (U(1) << 24)
32 #define MPIDR_AFFINITY_BITS U(8)
33 #define MPIDR_AFFLVL_MASK U(0xff)
34 #define MPIDR_AFF0_SHIFT U(0)
35 #define MPIDR_AFF1_SHIFT U(8)
36 #define MPIDR_AFF2_SHIFT U(16)
37 #define MPIDR_AFF3_SHIFT U(32)
38 #define MPIDR_AFFINITY_MASK U(0xff00ffffff)
39 #define MPIDR_AFFLVL_SHIFT U(3)
40 #define MPIDR_AFFLVL0 U(0)
41 #define MPIDR_AFFLVL1 U(1)
42 #define MPIDR_AFFLVL2 U(2)
43 #define MPIDR_AFFLVL3 U(3)
57 #define MPIDR_MAX_AFFLVL U(2)
60 #define FIRST_MPIDR U(0)
85 #define CNTCR_OFF U(0x000)
86 #define CNTFID_OFF U(0x020)
88 #define CNTCR_EN (U(1) << 0)
89 #define CNTCR_HDBG (U(1) << 1)
96 #define LOUIS_SHIFT U(21)
97 #define LOC_SHIFT U(24)
98 #define CLIDR_FIELD_WIDTH U(3)
101 #define LEVEL_SHIFT U(1)
104 #define DCISW U(0x0)
105 #define DCCISW U(0x1)
106 #define DCCSW U(0x2)
109 #define ID_AA64PFR0_EL0_SHIFT U(0)
110 #define ID_AA64PFR0_EL1_SHIFT U(4)
111 #define ID_AA64PFR0_EL2_SHIFT U(8)
112 #define ID_AA64PFR0_EL3_SHIFT U(12)
113 #define ID_AA64PFR0_ELX_MASK U(0xf)
116 #define ID_AA64DFR0_PMS_SHIFT U(32)
117 #define ID_AA64DFR0_PMS_LENGTH U(4)
118 #define ID_AA64DFR0_PMS_MASK U(0xf)
120 #define EL_IMPL_NONE U(0)
121 #define EL_IMPL_A64ONLY U(1)
122 #define EL_IMPL_A64_A32 U(2)
124 #define ID_AA64PFR0_GIC_SHIFT U(24)
125 #define ID_AA64PFR0_GIC_WIDTH U(4)
126 #define ID_AA64PFR0_GIC_MASK ((U(1) << ID_AA64PFR0_GIC_WIDTH) - 1)
129 #define ID_AA64MMFR0_EL1_PARANGE_MASK U(0xf)
131 #define PARANGE_0000 U(32)
132 #define PARANGE_0001 U(36)
133 #define PARANGE_0010 U(40)
134 #define PARANGE_0011 U(42)
135 #define PARANGE_0100 U(44)
136 #define PARANGE_0101 U(48)
139 #define ID_PFR1_VIRTEXT_SHIFT U(12)
140 #define ID_PFR1_VIRTEXT_MASK U(0xf)
145 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
146 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
147 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
149 #define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
150 (U(1) << 22) | (U(1) << 20) | (U(1) << 11))
152 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
153 (U(1) << 4) | (U(1) << 3))
155 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
156 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
157 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
159 #define SCTLR_M_BIT (U(1) << 0)
160 #define SCTLR_A_BIT (U(1) << 1)
161 #define SCTLR_C_BIT (U(1) << 2)
162 #define SCTLR_SA_BIT (U(1) << 3)
163 #define SCTLR_CP15BEN_BIT (U(1) << 5)
164 #define SCTLR_I_BIT (U(1) << 12)
165 #define SCTLR_NTWI_BIT (U(1) << 16)
166 #define SCTLR_NTWE_BIT (U(1) << 18)
167 #define SCTLR_WXN_BIT (U(1) << 19)
168 #define SCTLR_EE_BIT (U(1) << 25)
173 #define CPACR_EL1_FP_TRAP_EL0 U(0x1)
174 #define CPACR_EL1_FP_TRAP_ALL U(0x2)
175 #define CPACR_EL1_FP_TRAP_NONE U(0x3)
178 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
179 #define SCR_TWE_BIT (U(1) << 13)
180 #define SCR_TWI_BIT (U(1) << 12)
181 #define SCR_ST_BIT (U(1) << 11)
182 #define SCR_RW_BIT (U(1) << 10)
183 #define SCR_SIF_BIT (U(1) << 9)
184 #define SCR_HCE_BIT (U(1) << 8)
185 #define SCR_SMD_BIT (U(1) << 7)
186 #define SCR_EA_BIT (U(1) << 3)
187 #define SCR_FIQ_BIT (U(1) << 2)
188 #define SCR_IRQ_BIT (U(1) << 1)
189 #define SCR_NS_BIT (U(1) << 0)
190 #define SCR_VALID_BIT_MASK U(0x2f8f)
195 #define MDCR_SPD32_LEGACY U(0x0)
196 #define MDCR_SPD32_DISABLE U(0x2)
197 #define MDCR_SPD32_ENABLE U(0x3)
198 #define MDCR_SDD_BIT (U(1) << 16)
200 #define MDCR_NSPB_EL1 U(0x3)
201 #define MDCR_TDOSA_BIT (U(1) << 10)
202 #define MDCR_TDA_BIT (U(1) << 9)
203 #define MDCR_TPM_BIT (U(1) << 6)
204 #define MDCR_EL3_RESET_VAL U(0x0)
211 #define MDCR_EL2_TPMS (U(1) << 14)
213 #define MDCR_EL2_E2PB_EL1 U(0x3)
214 #define MDCR_EL2_TDRA_BIT (U(1) << 11)
215 #define MDCR_EL2_TDOSA_BIT (U(1) << 10)
216 #define MDCR_EL2_TDA_BIT (U(1) << 9)
217 #define MDCR_EL2_TDE_BIT (U(1) << 8)
218 #define MDCR_EL2_HPME_BIT (U(1) << 7)
219 #define MDCR_EL2_TPM_BIT (U(1) << 6)
220 #define MDCR_EL2_TPMCR_BIT (U(1) << 5)
221 #define MDCR_EL2_RESET_VAL U(0x0)
224 #define HSTR_EL2_RESET_VAL U(0x0)
225 #define HSTR_EL2_T_MASK U(0xff)
228 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
229 #define CNTHP_CTL_RESET_VAL U(0x0)
234 #define VTTBR_VMID_SHIFT U(48)
236 #define VTTBR_BADDR_SHIFT U(0)
239 #define HCR_RW_SHIFT U(31)
241 #define HCR_AMO_BIT (U(1) << 5)
242 #define HCR_IMO_BIT (U(1) << 4)
243 #define HCR_FMO_BIT (U(1) << 3)
246 #define ISR_A_SHIFT U(8)
247 #define ISR_I_SHIFT U(7)
248 #define ISR_F_SHIFT U(6)
251 #define CNTHCTL_RESET_VAL U(0x0)
252 #define EVNTEN_BIT (U(1) << 2)
253 #define EL1PCEN_BIT (U(1) << 1)
254 #define EL1PCTEN_BIT (U(1) << 0)
257 #define EL0PTEN_BIT (U(1) << 9)
258 #define EL0VTEN_BIT (U(1) << 8)
259 #define EL0PCTEN_BIT (U(1) << 0)
260 #define EL0VCTEN_BIT (U(1) << 1)
261 #define EVNTEN_BIT (U(1) << 2)
262 #define EVNTDIR_BIT (U(1) << 3)
263 #define EVNTI_SHIFT U(4)
264 #define EVNTI_MASK U(0xf)
267 #define TCPAC_BIT (U(1) << 31)
268 #define TTA_BIT (U(1) << 20)
269 #define TFP_BIT (U(1) << 10)
270 #define CPTR_EL3_RESET_VAL U(0x0)
273 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
274 #define CPTR_EL2_TCPAC_BIT (U(1) << 31)
275 #define CPTR_EL2_TTA_BIT (U(1) << 20)
276 #define CPTR_EL2_TFP_BIT (U(1) << 10)
280 #define DAIF_FIQ_BIT (U(1) << 0)
281 #define DAIF_IRQ_BIT (U(1) << 1)
282 #define DAIF_ABT_BIT (U(1) << 2)
283 #define DAIF_DBG_BIT (U(1) << 3)
284 #define SPSR_DAIF_SHIFT U(6)
285 #define SPSR_DAIF_MASK U(0xf)
287 #define SPSR_AIF_SHIFT U(6)
288 #define SPSR_AIF_MASK U(0x7)
290 #define SPSR_E_SHIFT U(9)
291 #define SPSR_E_MASK U(0x1)
292 #define SPSR_E_LITTLE U(0x0)
293 #define SPSR_E_BIG U(0x1)
295 #define SPSR_T_SHIFT U(5)
296 #define SPSR_T_MASK U(0x1)
297 #define SPSR_T_ARM U(0x0)
298 #define SPSR_T_THUMB U(0x1)
306 #define RMR_EL3_RR_BIT (U(1) << 1)
307 #define RMR_EL3_AA64_BIT (U(1) << 0)
312 #define HI_VECTOR_BASE U(0xFFFF0000)
317 #define TCR_EL3_RES1 ((U(1) << 31) | (U(1) << 23))
318 #define TCR_EL1_IPS_SHIFT U(32)
319 #define TCR_EL3_PS_SHIFT U(16)
321 #define TCR_TxSZ_MIN U(16)
322 #define TCR_TxSZ_MAX U(39)
325 #define TCR_PS_BITS_4GB U(0x0)
326 #define TCR_PS_BITS_64GB U(0x1)
327 #define TCR_PS_BITS_1TB U(0x2)
328 #define TCR_PS_BITS_4TB U(0x3)
329 #define TCR_PS_BITS_16TB U(0x4)
330 #define TCR_PS_BITS_256TB U(0x5)
339 #define TCR_RGN_INNER_NC (U(0x0) << 8)
340 #define TCR_RGN_INNER_WBA (U(0x1) << 8)
341 #define TCR_RGN_INNER_WT (U(0x2) << 8)
342 #define TCR_RGN_INNER_WBNA (U(0x3) << 8)
344 #define TCR_RGN_OUTER_NC (U(0x0) << 10)
345 #define TCR_RGN_OUTER_WBA (U(0x1) << 10)
346 #define TCR_RGN_OUTER_WT (U(0x2) << 10)
347 #define TCR_RGN_OUTER_WBNA (U(0x3) << 10)
349 #define TCR_SH_NON_SHAREABLE (U(0x0) << 12)
350 #define TCR_SH_OUTER_SHAREABLE (U(0x2) << 12)
351 #define TCR_SH_INNER_SHAREABLE (U(0x3) << 12)
353 #define TCR_EPD1_BIT (U(1) << 23)
355 #define MODE_SP_SHIFT U(0x0)
356 #define MODE_SP_MASK U(0x1)
357 #define MODE_SP_EL0 U(0x0)
358 #define MODE_SP_ELX U(0x1)
360 #define MODE_RW_SHIFT U(0x4)
361 #define MODE_RW_MASK U(0x1)
362 #define MODE_RW_64 U(0x0)
363 #define MODE_RW_32 U(0x1)
365 #define MODE_EL_SHIFT U(0x2)
366 #define MODE_EL_MASK U(0x3)
367 #define MODE_EL3 U(0x3)
368 #define MODE_EL2 U(0x2)
369 #define MODE_EL1 U(0x1)
370 #define MODE_EL0 U(0x0)
372 #define MODE32_SHIFT U(0)
373 #define MODE32_MASK U(0xf)
374 #define MODE32_usr U(0x0)
375 #define MODE32_fiq U(0x1)
376 #define MODE32_irq U(0x2)
377 #define MODE32_svc U(0x3)
378 #define MODE32_mon U(0x6)
379 #define MODE32_abt U(0x7)
380 #define MODE32_hyp U(0xa)
381 #define MODE32_und U(0xb)
382 #define MODE32_sys U(0xf)
410 #define CTR_CWG_SHIFT U(24)
411 #define CTR_CWG_MASK U(0xf)
412 #define CTR_ERG_SHIFT U(20)
413 #define CTR_ERG_MASK U(0xf)
414 #define CTR_DMINLINE_SHIFT U(16)
415 #define CTR_DMINLINE_MASK U(0xf)
416 #define CTR_L1IP_SHIFT U(14)
417 #define CTR_L1IP_MASK U(0x3)
418 #define CTR_IMINLINE_SHIFT U(0)
419 #define CTR_IMINLINE_MASK U(0xf)
421 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
424 #define CNTP_CTL_ENABLE_SHIFT U(0)
425 #define CNTP_CTL_IMASK_SHIFT U(1)
426 #define CNTP_CTL_ISTATUS_SHIFT U(2)
428 #define CNTP_CTL_ENABLE_MASK U(1)
429 #define CNTP_CTL_IMASK_MASK U(1)
430 #define CNTP_CTL_ISTATUS_MASK U(1)
439 #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
440 #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
442 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
443 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
446 #define ESR_EC_SHIFT U(26)
447 #define ESR_EC_MASK U(0x3f)
448 #define ESR_EC_LENGTH U(6)
449 #define EC_UNKNOWN U(0x0)
450 #define EC_WFE_WFI U(0x1)
451 #define EC_AARCH32_CP15_MRC_MCR U(0x3)
452 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
453 #define EC_AARCH32_CP14_MRC_MCR U(0x5)
454 #define EC_AARCH32_CP14_LDC_STC U(0x6)
455 #define EC_FP_SIMD U(0x7)
456 #define EC_AARCH32_CP10_MRC U(0x8)
457 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
458 #define EC_ILLEGAL U(0xe)
459 #define EC_AARCH32_SVC U(0x11)
460 #define EC_AARCH32_HVC U(0x12)
461 #define EC_AARCH32_SMC U(0x13)
462 #define EC_AARCH64_SVC U(0x15)
463 #define EC_AARCH64_HVC U(0x16)
464 #define EC_AARCH64_SMC U(0x17)
465 #define EC_AARCH64_SYS U(0x18)
466 #define EC_IABORT_LOWER_EL U(0x20)
467 #define EC_IABORT_CUR_EL U(0x21)
468 #define EC_PC_ALIGN U(0x22)
469 #define EC_DABORT_LOWER_EL U(0x24)
470 #define EC_DABORT_CUR_EL U(0x25)
471 #define EC_SP_ALIGN U(0x26)
472 #define EC_AARCH32_FP U(0x28)
473 #define EC_AARCH64_FP U(0x2c)
474 #define EC_SERROR U(0x2f)
479 #define RMR_RESET_REQUEST_SHIFT U(0x1)
480 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
487 #define TLBI_ADDR_SHIFT U(12)
495 #define CNTNSAR U(0x4)
498 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
499 #define CNTACR_RPCT_SHIFT U(0x0)
500 #define CNTACR_RVCT_SHIFT U(0x1)
501 #define CNTACR_RFRQ_SHIFT U(0x2)
502 #define CNTACR_RVOFF_SHIFT U(0x3)
503 #define CNTACR_RWVT_SHIFT U(0x4)
504 #define CNTACR_RWPT_SHIFT U(0x5)
507 #define PMCR_EL0_RESET_VAL U(0x0)
508 #define PMCR_EL0_N_SHIFT U(11)
509 #define PMCR_EL0_N_MASK U(0x1f)
511 #define PMCR_EL0_LC_BIT (U(1) << 6)
512 #define PMCR_EL0_DP_BIT (U(1) << 5)
513 #define PMCR_EL0_X_BIT (U(1) << 4)
514 #define PMCR_EL0_D_BIT (U(1) << 3)