111 static uintptr_t qspi_base(void)  in qspi_base()  function
120 	while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_BUSY) != 0U) {  in stm32_qspi_wait_for_not_busy()
140 	while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TCF) == 0U) {  in stm32_qspi_wait_cmd()
148 		if ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TEF) != 0U) {  in stm32_qspi_wait_cmd()
157 	mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF | QSPI_FCR_CTEF);  in stm32_qspi_wait_cmd()
189 		while ((mmio_read_32(qspi_base() + QSPI_SR) &  in stm32_qspi_poll()
197 		fifo(buf++, qspi_base() + QSPI_DR);  in stm32_qspi_poll()
264 		mmio_write_32(qspi_base() + QSPI_DLR, op->data.nbytes - 1U);  in stm32_qspi_exec_op()
287 	mmio_write_32(qspi_base() + QSPI_CCR, ccr);  in stm32_qspi_exec_op()
290 		mmio_write_32(qspi_base() + QSPI_AR, op->addr.val);  in stm32_qspi_exec_op()
315 	mmio_setbits_32(qspi_base() + QSPI_CR, QSPI_CR_ABORT);  in stm32_qspi_exec_op()
319 	while ((mmio_read_32(qspi_base() + QSPI_CR) & QSPI_CR_ABORT) != 0U) {  in stm32_qspi_exec_op()
326 	mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF);  in stm32_qspi_exec_op()
349 	mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_FSEL, cr);  in stm32_qspi_claim_bus()
356 	mmio_clrbits_32(qspi_base() + QSPI_CR, QSPI_CR_EN);  in stm32_qspi_release_bus()
385 	mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_PRESCALER_MASK,  in stm32_qspi_set_speed()
388 	mmio_clrsetbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CSHT_MASK, csht);  in stm32_qspi_set_speed()
409 		mmio_setbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE);  in stm32_qspi_set_mode()
411 		mmio_clrbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE);  in stm32_qspi_set_mode()
496 	mmio_write_32(qspi_base() + QSPI_CR, QSPI_CR_SSHIFT);  in stm32_qspi_init()
497 	mmio_write_32(qspi_base() + QSPI_DCR, QSPI_DCR_FSIZE_MASK);  in stm32_qspi_init()