Lines Matching refs:U
15 #define MIDR_IMPL_MASK U(0xff)
16 #define MIDR_IMPL_SHIFT U(24)
17 #define MIDR_VAR_SHIFT U(20)
18 #define MIDR_VAR_BITS U(4)
19 #define MIDR_REV_SHIFT U(0)
20 #define MIDR_REV_BITS U(4)
21 #define MIDR_PN_MASK U(0xfff)
22 #define MIDR_PN_SHIFT U(4)
27 #define MPIDR_MT_MASK (U(1) << 24)
30 #define MPIDR_AFFINITY_BITS U(8)
31 #define MPIDR_AFFLVL_MASK U(0xff)
32 #define MPIDR_AFFLVL_SHIFT U(3)
33 #define MPIDR_AFF0_SHIFT U(0)
34 #define MPIDR_AFF1_SHIFT U(8)
35 #define MPIDR_AFF2_SHIFT U(16)
37 #define MPIDR_AFFINITY_MASK U(0x00ffffff)
38 #define MPIDR_AFFLVL0 U(0)
39 #define MPIDR_AFFLVL1 U(1)
40 #define MPIDR_AFFLVL2 U(2)
49 #define MPIDR_AFFLVL3_VAL(mpidr) U(0)
63 #define INVALID_MPID U(0xFFFFFFFF)
69 #define MPIDR_MAX_AFFLVL U(2)
72 #define DC_OP_ISW U(0x0)
73 #define DC_OP_CISW U(0x1)
77 #define DC_OP_CSW U(0x2)
83 #define CNTCR_OFF U(0x000)
85 #define CNTCVL_OFF U(0x008)
87 #define CNTCVU_OFF U(0x00C)
88 #define CNTFID_OFF U(0x020)
90 #define CNTCR_EN (U(1) << 0)
91 #define CNTCR_HDBG (U(1) << 1)
98 #define LOUIS_SHIFT U(21)
99 #define LOC_SHIFT U(24)
100 #define CLIDR_FIELD_WIDTH U(3)
103 #define LEVEL_SHIFT U(1)
106 #define ID_MMFR4_CNP_SHIFT U(12)
107 #define ID_MMFR4_CNP_LENGTH U(4)
108 #define ID_MMFR4_CNP_MASK U(0xf)
111 #define ID_PFR0_AMU_SHIFT U(20)
112 #define ID_PFR0_AMU_LENGTH U(4)
113 #define ID_PFR0_AMU_MASK U(0xf)
115 #define ID_PFR0_DIT_SHIFT U(24)
116 #define ID_PFR0_DIT_LENGTH U(4)
117 #define ID_PFR0_DIT_MASK U(0xf)
118 #define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT)
121 #define ID_PFR1_VIRTEXT_SHIFT U(12)
122 #define ID_PFR1_VIRTEXT_MASK U(0xf)
125 #define ID_PFR1_GENTIMER_SHIFT U(16)
126 #define ID_PFR1_GENTIMER_MASK U(0xf)
127 #define ID_PFR1_GIC_SHIFT U(28)
128 #define ID_PFR1_GIC_MASK U(0xf)
131 #define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
132 (U(1) << 3))
136 #define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11))
138 #define SCTLR_M_BIT (U(1) << 0)
139 #define SCTLR_A_BIT (U(1) << 1)
140 #define SCTLR_C_BIT (U(1) << 2)
141 #define SCTLR_CP15BEN_BIT (U(1) << 5)
142 #define SCTLR_ITD_BIT (U(1) << 7)
143 #define SCTLR_Z_BIT (U(1) << 11)
144 #define SCTLR_I_BIT (U(1) << 12)
145 #define SCTLR_V_BIT (U(1) << 13)
146 #define SCTLR_RR_BIT (U(1) << 14)
147 #define SCTLR_NTWI_BIT (U(1) << 16)
148 #define SCTLR_NTWE_BIT (U(1) << 18)
149 #define SCTLR_WXN_BIT (U(1) << 19)
150 #define SCTLR_UWXN_BIT (U(1) << 20)
151 #define SCTLR_EE_BIT (U(1) << 25)
152 #define SCTLR_TRE_BIT (U(1) << 28)
153 #define SCTLR_AFE_BIT (U(1) << 29)
154 #define SCTLR_TE_BIT (U(1) << 30)
155 #define SCTLR_DSSBS_BIT (U(1) << 31)
161 #define SDCR_SPD_LEGACY U(0x0)
162 #define SDCR_SPD_DISABLE U(0x2)
163 #define SDCR_SPD_ENABLE U(0x3)
164 #define SDCR_SCCD_BIT (U(1) << 23)
165 #define SDCR_SPME_BIT (U(1) << 17)
166 #define SDCR_RESET_VAL U(0x0)
169 #define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
170 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
171 (U(1) << 11) | (U(1) << 4) | (U(1) << 3))
173 #define HSCTLR_M_BIT (U(1) << 0)
174 #define HSCTLR_A_BIT (U(1) << 1)
175 #define HSCTLR_C_BIT (U(1) << 2)
176 #define HSCTLR_CP15BEN_BIT (U(1) << 5)
177 #define HSCTLR_ITD_BIT (U(1) << 7)
178 #define HSCTLR_SED_BIT (U(1) << 8)
179 #define HSCTLR_I_BIT (U(1) << 12)
180 #define HSCTLR_WXN_BIT (U(1) << 19)
181 #define HSCTLR_EE_BIT (U(1) << 25)
182 #define HSCTLR_TE_BIT (U(1) << 30)
186 #define CPACR_FP_TRAP_PL0 U(0x1)
187 #define CPACR_FP_TRAP_ALL U(0x2)
188 #define CPACR_FP_TRAP_NONE U(0x3)
191 #define SCR_TWE_BIT (U(1) << 13)
192 #define SCR_TWI_BIT (U(1) << 12)
193 #define SCR_SIF_BIT (U(1) << 9)
194 #define SCR_HCE_BIT (U(1) << 8)
195 #define SCR_SCD_BIT (U(1) << 7)
196 #define SCR_NET_BIT (U(1) << 6)
197 #define SCR_AW_BIT (U(1) << 5)
198 #define SCR_FW_BIT (U(1) << 4)
199 #define SCR_EA_BIT (U(1) << 3)
200 #define SCR_FIQ_BIT (U(1) << 2)
201 #define SCR_IRQ_BIT (U(1) << 1)
202 #define SCR_NS_BIT (U(1) << 0)
203 #define SCR_VALID_BIT_MASK U(0x33ff)
204 #define SCR_RESET_VAL U(0x0)
209 #define HCR_TGE_BIT (U(1) << 27)
210 #define HCR_AMO_BIT (U(1) << 5)
211 #define HCR_IMO_BIT (U(1) << 4)
212 #define HCR_FMO_BIT (U(1) << 3)
213 #define HCR_RESET_VAL U(0x0)
216 #define CNTHCTL_RESET_VAL U(0x0)
217 #define PL1PCEN_BIT (U(1) << 1)
218 #define PL1PCTEN_BIT (U(1) << 0)
221 #define PL0PTEN_BIT (U(1) << 9)
222 #define PL0VTEN_BIT (U(1) << 8)
223 #define PL0PCTEN_BIT (U(1) << 0)
224 #define PL0VCTEN_BIT (U(1) << 1)
225 #define EVNTEN_BIT (U(1) << 2)
226 #define EVNTDIR_BIT (U(1) << 3)
227 #define EVNTI_SHIFT U(4)
228 #define EVNTI_MASK U(0xf)
231 #define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff))
232 #define TCPAC_BIT (U(1) << 31)
233 #define TAM_BIT (U(1) << 30)
234 #define TTA_BIT (U(1) << 20)
235 #define TCP11_BIT (U(1) << 11)
236 #define TCP10_BIT (U(1) << 10)
242 #define VTTBR_VMID_SHIFT U(48)
244 #define VTTBR_BADDR_SHIFT U(0)
247 #define HDCR_HLP_BIT (U(1) << 26)
248 #define HDCR_HPME_BIT (U(1) << 7)
249 #define HDCR_RESET_VAL U(0x0)
252 #define HSTR_RESET_VAL U(0x0)
255 #define CNTHP_CTL_RESET_VAL U(0x0)
258 #define NSASEDIS_BIT (U(1) << 15)
259 #define NSTRCDIS_BIT (U(1) << 20)
260 #define NSACR_CP11_BIT (U(1) << 11)
261 #define NSACR_CP10_BIT (U(1) << 10)
262 #define NSACR_IMP_DEF_MASK (U(0x7) << 16)
264 #define NSACR_RESET_VAL U(0x0)
267 #define ASEDIS_BIT (U(1) << 31)
268 #define TRCDIS_BIT (U(1) << 28)
269 #define CPACR_CP11_SHIFT U(22)
270 #define CPACR_CP10_SHIFT U(20)
271 #define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\
272 (U(0x3) << CPACR_CP10_SHIFT))
273 #define CPACR_RESET_VAL U(0x0)
276 #define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8))
277 #define FPEXC_EN_BIT (U(1) << 30)
281 #define SPSR_FIQ_BIT (U(1) << 0)
282 #define SPSR_IRQ_BIT (U(1) << 1)
283 #define SPSR_ABT_BIT (U(1) << 2)
284 #define SPSR_AIF_SHIFT U(6)
285 #define SPSR_AIF_MASK U(0x7)
287 #define SPSR_E_SHIFT U(9)
288 #define SPSR_E_MASK U(0x1)
289 #define SPSR_E_LITTLE U(0)
290 #define SPSR_E_BIG U(1)
292 #define SPSR_T_SHIFT U(5)
293 #define SPSR_T_MASK U(0x1)
294 #define SPSR_T_ARM U(0)
295 #define SPSR_T_THUMB U(1)
297 #define SPSR_MODE_SHIFT U(0)
298 #define SPSR_MODE_MASK U(0x7)
305 #define CPSR_DIT_BIT (U(1) << 21)
309 #define TTBCR_EAE_BIT (U(1) << 31)
311 #define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28)
312 #define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28)
313 #define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28)
315 #define TTBCR_RGN1_OUTER_NC (U(0x0) << 26)
316 #define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26)
317 #define TTBCR_RGN1_OUTER_WT (U(0x2) << 26)
318 #define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26)
320 #define TTBCR_RGN1_INNER_NC (U(0x0) << 24)
321 #define TTBCR_RGN1_INNER_WBA (U(0x1) << 24)
322 #define TTBCR_RGN1_INNER_WT (U(0x2) << 24)
323 #define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24)
325 #define TTBCR_EPD1_BIT (U(1) << 23)
326 #define TTBCR_A1_BIT (U(1) << 22)
328 #define TTBCR_T1SZ_SHIFT U(16)
329 #define TTBCR_T1SZ_MASK U(0x7)
330 #define TTBCR_TxSZ_MIN U(0)
331 #define TTBCR_TxSZ_MAX U(7)
333 #define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12)
334 #define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
335 #define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
337 #define TTBCR_RGN0_OUTER_NC (U(0x0) << 10)
338 #define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10)
339 #define TTBCR_RGN0_OUTER_WT (U(0x2) << 10)
340 #define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10)
342 #define TTBCR_RGN0_INNER_NC (U(0x0) << 8)
343 #define TTBCR_RGN0_INNER_WBA (U(0x1) << 8)
344 #define TTBCR_RGN0_INNER_WT (U(0x2) << 8)
345 #define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8)
347 #define TTBCR_EPD0_BIT (U(1) << 7)
348 #define TTBCR_T0SZ_SHIFT U(0)
349 #define TTBCR_T0SZ_MASK U(0x7)
354 #define HTCR_RES1 ((U(1) << 31) | (U(1) << 23))
356 #define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12)
357 #define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
358 #define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
360 #define HTCR_RGN0_OUTER_NC (U(0x0) << 10)
361 #define HTCR_RGN0_OUTER_WBA (U(0x1) << 10)
362 #define HTCR_RGN0_OUTER_WT (U(0x2) << 10)
363 #define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10)
365 #define HTCR_RGN0_INNER_NC (U(0x0) << 8)
366 #define HTCR_RGN0_INNER_WBA (U(0x1) << 8)
367 #define HTCR_RGN0_INNER_WT (U(0x2) << 8)
368 #define HTCR_RGN0_INNER_WBNA (U(0x3) << 8)
370 #define HTCR_T0SZ_SHIFT U(0)
371 #define HTCR_T0SZ_MASK U(0x7)
373 #define MODE_RW_SHIFT U(0x4)
374 #define MODE_RW_MASK U(0x1)
375 #define MODE_RW_32 U(0x1)
377 #define MODE32_SHIFT U(0)
378 #define MODE32_MASK U(0x1f)
379 #define MODE32_usr U(0x10)
380 #define MODE32_fiq U(0x11)
381 #define MODE32_irq U(0x12)
382 #define MODE32_svc U(0x13)
383 #define MODE32_mon U(0x16)
384 #define MODE32_abt U(0x17)
385 #define MODE32_hyp U(0x1a)
386 #define MODE32_und U(0x1b)
387 #define MODE32_sys U(0x1f)
407 #define CTR_CWG_SHIFT U(24)
408 #define CTR_CWG_MASK U(0xf)
409 #define CTR_ERG_SHIFT U(20)
410 #define CTR_ERG_MASK U(0xf)
411 #define CTR_DMINLINE_SHIFT U(16)
412 #define CTR_DMINLINE_WIDTH U(4)
413 #define CTR_DMINLINE_MASK ((U(1) << 4) - U(1))
414 #define CTR_L1IP_SHIFT U(14)
415 #define CTR_L1IP_MASK U(0x3)
416 #define CTR_IMINLINE_SHIFT U(0)
417 #define CTR_IMINLINE_MASK U(0xf)
419 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
422 #define PMCR_N_SHIFT U(11)
423 #define PMCR_N_MASK U(0x1f)
425 #define PMCR_LP_BIT (U(1) << 7)
426 #define PMCR_LC_BIT (U(1) << 6)
427 #define PMCR_DP_BIT (U(1) << 5)
428 #define PMCR_RESET_VAL U(0x0)
435 #define TLBI_ADDR_SHIFT U(0)
436 #define TLBI_ADDR_MASK U(0xFFFFF000)
443 #define CNTCTLBASE_CNTFRQ U(0x0)
444 #define CNTNSAR U(0x4)
447 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
448 #define CNTACR_RPCT_SHIFT U(0x0)
449 #define CNTACR_RVCT_SHIFT U(0x1)
450 #define CNTACR_RFRQ_SHIFT U(0x2)
451 #define CNTACR_RVOFF_SHIFT U(0x3)
452 #define CNTACR_RWVT_SHIFT U(0x4)
453 #define CNTACR_RWPT_SHIFT U(0x5)
460 #define CNTPCT_LO U(0x0)
462 #define CNTBASEN_CNTFRQ U(0x10)
464 #define CNTP_CVAL_LO U(0x20)
466 #define CNTP_CTL U(0x2c)
473 #define CNTP_CTL_ENABLE_MASK U(1)
474 #define CNTP_CTL_IMASK_MASK U(1)
475 #define CNTP_CTL_ISTATUS_MASK U(1)
478 #define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3)))
479 #define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3)))
590 #define MAIR_DEV_nGnRnE U(0x0)
591 #define MAIR_DEV_nGnRE U(0x4)
592 #define MAIR_DEV_nGRE U(0x8)
593 #define MAIR_DEV_GRE U(0xc)
613 #define MAIR_NORM_WT_TR_WA U(0x1)
614 #define MAIR_NORM_WT_TR_RA U(0x2)
615 #define MAIR_NORM_WT_TR_RWA U(0x3)
616 #define MAIR_NORM_NC U(0x4)
617 #define MAIR_NORM_WB_TR_WA U(0x5)
618 #define MAIR_NORM_WB_TR_RA U(0x6)
619 #define MAIR_NORM_WB_TR_RWA U(0x7)
620 #define MAIR_NORM_WT_NTR_NA U(0x8)
621 #define MAIR_NORM_WT_NTR_WA U(0x9)
622 #define MAIR_NORM_WT_NTR_RA U(0xa)
623 #define MAIR_NORM_WT_NTR_RWA U(0xb)
624 #define MAIR_NORM_WB_NTR_NA U(0xc)
625 #define MAIR_NORM_WB_NTR_WA U(0xd)
626 #define MAIR_NORM_WB_NTR_RA U(0xe)
627 #define MAIR_NORM_WB_NTR_RWA U(0xf)
629 #define MAIR_NORM_OUTER_SHIFT U(4)
635 #define PAR_F_SHIFT U(0)
637 #define PAR_ADDR_SHIFT U(12)