Lines Matching refs:ULL
29 #define MPIDR_MT_MASK (ULL(1) << 24)
33 #define MPIDR_AFFLVL_MASK ULL(0xff)
39 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
41 #define MPIDR_AFFLVL0 ULL(0x0)
42 #define MPIDR_AFFLVL1 ULL(0x1)
43 #define MPIDR_AFFLVL2 ULL(0x2)
44 #define MPIDR_AFFLVL3 ULL(0x3)
136 #define ID_AA64PFR0_AMU_MASK ULL(0xf)
137 #define ID_AA64PFR0_ELX_MASK ULL(0xf)
140 #define ID_AA64PFR0_GIC_MASK ULL(0xf)
142 #define ID_AA64PFR0_SVE_MASK ULL(0xf)
144 #define ID_AA64PFR0_SEL2_MASK ULL(0xf)
146 #define ID_AA64PFR0_MPAM_MASK ULL(0xf)
148 #define ID_AA64PFR0_DIT_MASK ULL(0xf)
152 #define ID_AA64PFR0_CSV2_MASK ULL(0xf)
156 #define EL_IMPL_NONE ULL(0)
157 #define EL_IMPL_A64ONLY ULL(1)
158 #define EL_IMPL_A64_A32 ULL(2)
162 #define ID_AA64DFR0_PMS_MASK ULL(0xf)
167 #define ID_AA64ISAR1_GPI_MASK ULL(0xf)
169 #define ID_AA64ISAR1_GPA_MASK ULL(0xf)
171 #define ID_AA64ISAR1_API_MASK ULL(0xf)
173 #define ID_AA64ISAR1_APA_MASK ULL(0xf)
177 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
188 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
189 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
190 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
193 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
194 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
195 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
198 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
199 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
200 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
206 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf)
209 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
213 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
215 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
218 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
220 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
223 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
225 #define MTE_UNIMPLEMENTED ULL(0)
226 #define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */
227 #define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */
250 #define SCTLR_M_BIT (ULL(1) << 0)
251 #define SCTLR_A_BIT (ULL(1) << 1)
252 #define SCTLR_C_BIT (ULL(1) << 2)
253 #define SCTLR_SA_BIT (ULL(1) << 3)
254 #define SCTLR_SA0_BIT (ULL(1) << 4)
255 #define SCTLR_CP15BEN_BIT (ULL(1) << 5)
256 #define SCTLR_ITD_BIT (ULL(1) << 7)
257 #define SCTLR_SED_BIT (ULL(1) << 8)
258 #define SCTLR_UMA_BIT (ULL(1) << 9)
259 #define SCTLR_I_BIT (ULL(1) << 12)
260 #define SCTLR_EnDB_BIT (ULL(1) << 13)
261 #define SCTLR_DZE_BIT (ULL(1) << 14)
262 #define SCTLR_UCT_BIT (ULL(1) << 15)
263 #define SCTLR_NTWI_BIT (ULL(1) << 16)
264 #define SCTLR_NTWE_BIT (ULL(1) << 18)
265 #define SCTLR_WXN_BIT (ULL(1) << 19)
266 #define SCTLR_UWXN_BIT (ULL(1) << 20)
267 #define SCTLR_IESB_BIT (ULL(1) << 21)
268 #define SCTLR_E0E_BIT (ULL(1) << 24)
269 #define SCTLR_EE_BIT (ULL(1) << 25)
270 #define SCTLR_UCI_BIT (ULL(1) << 26)
271 #define SCTLR_EnDA_BIT (ULL(1) << 27)
272 #define SCTLR_EnIB_BIT (ULL(1) << 30)
273 #define SCTLR_EnIA_BIT (ULL(1) << 31)
274 #define SCTLR_BT0_BIT (ULL(1) << 35)
275 #define SCTLR_BT1_BIT (ULL(1) << 36)
276 #define SCTLR_BT_BIT (ULL(1) << 36)
277 #define SCTLR_DSSBS_BIT (ULL(1) << 44)
308 #define MDCR_SCCD_BIT (ULL(1) << 23)
309 #define MDCR_SPME_BIT (ULL(1) << 17)
310 #define MDCR_SDD_BIT (ULL(1) << 16)
312 #define MDCR_SPD32_LEGACY ULL(0x0)
313 #define MDCR_SPD32_DISABLE ULL(0x2)
314 #define MDCR_SPD32_ENABLE ULL(0x3)
316 #define MDCR_NSPB_EL1 ULL(0x3)
317 #define MDCR_TDOSA_BIT (ULL(1) << 10)
318 #define MDCR_TDA_BIT (ULL(1) << 9)
319 #define MDCR_TPM_BIT (ULL(1) << 6)
320 #define MDCR_EL3_RESET_VAL ULL(0x0)
348 #define VTTBR_RESET_VAL ULL(0x0)
349 #define VTTBR_VMID_MASK ULL(0xff)
351 #define VTTBR_BADDR_MASK ULL(0xffffffffffff)
355 #define HCR_API_BIT (ULL(1) << 41)
356 #define HCR_APK_BIT (ULL(1) << 40)
357 #define HCR_TGE_BIT (ULL(1) << 27)
359 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
360 #define HCR_AMO_BIT (ULL(1) << 5)
361 #define HCR_IMO_BIT (ULL(1) << 4)
362 #define HCR_FMO_BIT (ULL(1) << 3)
450 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
451 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
456 #define TCR_TxSZ_MIN ULL(16)
457 #define TCR_TxSZ_MAX ULL(39)
458 #define TCR_TxSZ_MAX_TTST ULL(48)
464 #define TCR_PS_BITS_4GB ULL(0x0)
465 #define TCR_PS_BITS_64GB ULL(0x1)
466 #define TCR_PS_BITS_1TB ULL(0x2)
467 #define TCR_PS_BITS_4TB ULL(0x3)
468 #define TCR_PS_BITS_16TB ULL(0x4)
469 #define TCR_PS_BITS_256TB ULL(0x5)
471 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
472 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
473 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
474 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
475 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
476 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
478 #define TCR_RGN_INNER_NC (ULL(0x0) << 8)
479 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
480 #define TCR_RGN_INNER_WT (ULL(0x2) << 8)
481 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
483 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
484 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
485 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
486 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
488 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
489 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
490 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
492 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24)
493 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24)
494 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24)
495 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24)
497 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26)
498 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26)
499 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26)
500 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26)
502 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28)
503 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28)
504 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28)
507 #define TCR_TG0_MASK ULL(3)
508 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
509 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
510 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
513 #define TCR_TG1_MASK ULL(3)
514 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT)
515 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT)
516 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT)
518 #define TCR_EPD0_BIT (ULL(1) << 7)
519 #define TCR_EPD1_BIT (ULL(1) << 23)
573 #define TTBR_CNP_BIT ULL(0x1)
652 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
716 #define MAIR_DEV_nGnRnE ULL(0x0)
717 #define MAIR_DEV_nGnRE ULL(0x4)
718 #define MAIR_DEV_nGRE ULL(0x8)
719 #define MAIR_DEV_GRE ULL(0xc)
739 #define MAIR_NORM_WT_TR_WA ULL(0x1)
740 #define MAIR_NORM_WT_TR_RA ULL(0x2)
741 #define MAIR_NORM_WT_TR_RWA ULL(0x3)
742 #define MAIR_NORM_NC ULL(0x4)
743 #define MAIR_NORM_WB_TR_WA ULL(0x5)
744 #define MAIR_NORM_WB_TR_RA ULL(0x6)
745 #define MAIR_NORM_WB_TR_RWA ULL(0x7)
746 #define MAIR_NORM_WT_NTR_NA ULL(0x8)
747 #define MAIR_NORM_WT_NTR_WA ULL(0x9)
748 #define MAIR_NORM_WT_NTR_RA ULL(0xa)
749 #define MAIR_NORM_WT_NTR_RWA ULL(0xb)
750 #define MAIR_NORM_WB_NTR_NA ULL(0xc)
751 #define MAIR_NORM_WB_NTR_WA ULL(0xd)
752 #define MAIR_NORM_WB_NTR_RA ULL(0xe)
753 #define MAIR_NORM_WB_NTR_RWA ULL(0xf)
762 #define PAR_F_MASK ULL(0x1)
764 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
845 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
846 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
848 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
849 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48)
851 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)