Lines Matching refs:SPM_BASE
10 #define SPM_POWERON_CONFIG_SET (SPM_BASE + 0x000)
11 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x010)
12 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x014)
13 #define SPM_CLK_SETTLE (SPM_BASE + 0x100)
14 #define SPM_CA7_CPU1_PWR_CON (SPM_BASE + 0x218)
15 #define SPM_CA7_CPU2_PWR_CON (SPM_BASE + 0x21c)
16 #define SPM_CA7_CPU3_PWR_CON (SPM_BASE + 0x220)
17 #define SPM_CA7_CPU1_L1_PDN (SPM_BASE + 0x264)
18 #define SPM_CA7_CPU2_L1_PDN (SPM_BASE + 0x26c)
19 #define SPM_CA7_CPU3_L1_PDN (SPM_BASE + 0x274)
20 #define SPM_MD32_SRAM_CON (SPM_BASE + 0x2c8)
21 #define SPM_PCM_CON0 (SPM_BASE + 0x310)
22 #define SPM_PCM_CON1 (SPM_BASE + 0x314)
23 #define SPM_PCM_IM_PTR (SPM_BASE + 0x318)
24 #define SPM_PCM_IM_LEN (SPM_BASE + 0x31c)
25 #define SPM_PCM_REG_DATA_INI (SPM_BASE + 0x320)
26 #define SPM_PCM_EVENT_VECTOR0 (SPM_BASE + 0x340)
27 #define SPM_PCM_EVENT_VECTOR1 (SPM_BASE + 0x344)
28 #define SPM_PCM_EVENT_VECTOR2 (SPM_BASE + 0x348)
29 #define SPM_PCM_EVENT_VECTOR3 (SPM_BASE + 0x34c)
30 #define SPM_PCM_MAS_PAUSE_MASK (SPM_BASE + 0x354)
31 #define SPM_PCM_PWR_IO_EN (SPM_BASE + 0x358)
32 #define SPM_PCM_TIMER_VAL (SPM_BASE + 0x35c)
33 #define SPM_PCM_TIMER_OUT (SPM_BASE + 0x360)
34 #define SPM_PCM_REG0_DATA (SPM_BASE + 0x380)
35 #define SPM_PCM_REG1_DATA (SPM_BASE + 0x384)
36 #define SPM_PCM_REG2_DATA (SPM_BASE + 0x388)
37 #define SPM_PCM_REG3_DATA (SPM_BASE + 0x38c)
38 #define SPM_PCM_REG4_DATA (SPM_BASE + 0x390)
39 #define SPM_PCM_REG5_DATA (SPM_BASE + 0x394)
40 #define SPM_PCM_REG6_DATA (SPM_BASE + 0x398)
41 #define SPM_PCM_REG7_DATA (SPM_BASE + 0x39c)
42 #define SPM_PCM_REG8_DATA (SPM_BASE + 0x3a0)
43 #define SPM_PCM_REG9_DATA (SPM_BASE + 0x3a4)
44 #define SPM_PCM_REG10_DATA (SPM_BASE + 0x3a8)
45 #define SPM_PCM_REG11_DATA (SPM_BASE + 0x3ac)
46 #define SPM_PCM_REG12_DATA (SPM_BASE + 0x3b0)
47 #define SPM_PCM_REG13_DATA (SPM_BASE + 0x3b4)
48 #define SPM_PCM_REG14_DATA (SPM_BASE + 0x3b8)
49 #define SPM_PCM_REG15_DATA (SPM_BASE + 0x3bc)
50 #define SPM_PCM_EVENT_REG_STA (SPM_BASE + 0x3c0)
51 #define SPM_PCM_FSM_STA (SPM_BASE + 0x3c4)
52 #define SPM_PCM_IM_HOST_RW_PTR (SPM_BASE + 0x3c8)
53 #define SPM_PCM_IM_HOST_RW_DAT (SPM_BASE + 0x3cc)
54 #define SPM_PCM_EVENT_VECTOR4 (SPM_BASE + 0x3d0)
55 #define SPM_PCM_EVENT_VECTOR5 (SPM_BASE + 0x3d4)
56 #define SPM_PCM_EVENT_VECTOR6 (SPM_BASE + 0x3d8)
57 #define SPM_PCM_EVENT_VECTOR7 (SPM_BASE + 0x3dc)
58 #define SPM_PCM_SW_INT_SET (SPM_BASE + 0x3e0)
59 #define SPM_PCM_SW_INT_CLEAR (SPM_BASE + 0x3e4)
60 #define SPM_CLK_CON (SPM_BASE + 0x400)
61 #define SPM_SLEEP_PTPOD2_CON (SPM_BASE + 0x408)
62 #define SPM_APMCU_PWRCTL (SPM_BASE + 0x600)
63 #define SPM_AP_DVFS_CON_SET (SPM_BASE + 0x604)
64 #define SPM_AP_STANBY_CON (SPM_BASE + 0x608)
65 #define SPM_PWR_STATUS (SPM_BASE + 0x60c)
66 #define SPM_PWR_STATUS_2ND (SPM_BASE + 0x610)
67 #define SPM_AP_BSI_REQ (SPM_BASE + 0x614)
68 #define SPM_SLEEP_TIMER_STA (SPM_BASE + 0x720)
69 #define SPM_SLEEP_WAKEUP_EVENT_MASK (SPM_BASE + 0x810)
70 #define SPM_SLEEP_CPU_WAKEUP_EVENT (SPM_BASE + 0x814)
71 #define SPM_SLEEP_MD32_WAKEUP_EVENT_MASK (SPM_BASE + 0x818)
72 #define SPM_PCM_WDT_TIMER_VAL (SPM_BASE + 0x824)
73 #define SPM_PCM_WDT_TIMER_OUT (SPM_BASE + 0x828)
74 #define SPM_PCM_MD32_MAILBOX (SPM_BASE + 0x830)
75 #define SPM_PCM_MD32_IRQ (SPM_BASE + 0x834)
76 #define SPM_SLEEP_ISR_MASK (SPM_BASE + 0x900)
77 #define SPM_SLEEP_ISR_STATUS (SPM_BASE + 0x904)
78 #define SPM_SLEEP_ISR_RAW_STA (SPM_BASE + 0x910)
79 #define SPM_SLEEP_MD32_ISR_RAW_STA (SPM_BASE + 0x914)
80 #define SPM_SLEEP_WAKEUP_MISC (SPM_BASE + 0x918)
81 #define SPM_SLEEP_BUS_PROTECT_RDY (SPM_BASE + 0x91c)
82 #define SPM_SLEEP_SUBSYS_IDLE_STA (SPM_BASE + 0x920)
83 #define SPM_PCM_RESERVE (SPM_BASE + 0xb00)
84 #define SPM_PCM_RESERVE2 (SPM_BASE + 0xb04)
85 #define SPM_PCM_FLAGS (SPM_BASE + 0xb08)
86 #define SPM_PCM_SRC_REQ (SPM_BASE + 0xb0c)
87 #define SPM_PCM_DEBUG_CON (SPM_BASE + 0xb20)
88 #define SPM_CA7_CPU0_IRQ_MASK (SPM_BASE + 0xb30)
89 #define SPM_CA7_CPU1_IRQ_MASK (SPM_BASE + 0xb34)
90 #define SPM_CA7_CPU2_IRQ_MASK (SPM_BASE + 0xb38)
91 #define SPM_CA7_CPU3_IRQ_MASK (SPM_BASE + 0xb3c)
92 #define SPM_CA15_CPU0_IRQ_MASK (SPM_BASE + 0xb40)
93 #define SPM_CA15_CPU1_IRQ_MASK (SPM_BASE + 0xb44)
94 #define SPM_CA15_CPU2_IRQ_MASK (SPM_BASE + 0xb48)
95 #define SPM_CA15_CPU3_IRQ_MASK (SPM_BASE + 0xb4c)
96 #define SPM_PCM_PASR_DPD_0 (SPM_BASE + 0xb60)
97 #define SPM_PCM_PASR_DPD_1 (SPM_BASE + 0xb64)
98 #define SPM_PCM_PASR_DPD_2 (SPM_BASE + 0xb68)
99 #define SPM_PCM_PASR_DPD_3 (SPM_BASE + 0xb6c)
100 #define SPM_SLEEP_CA7_WFI0_EN (SPM_BASE + 0xf00)
101 #define SPM_SLEEP_CA7_WFI1_EN (SPM_BASE + 0xf04)
102 #define SPM_SLEEP_CA7_WFI2_EN (SPM_BASE + 0xf08)
103 #define SPM_SLEEP_CA7_WFI3_EN (SPM_BASE + 0xf0c)
104 #define SPM_SLEEP_CA15_WFI0_EN (SPM_BASE + 0xf10)
105 #define SPM_SLEEP_CA15_WFI1_EN (SPM_BASE + 0xf14)
106 #define SPM_SLEEP_CA15_WFI2_EN (SPM_BASE + 0xf18)
107 #define SPM_SLEEP_CA15_WFI3_EN (SPM_BASE + 0xf1c)