Lines Matching refs:Op0
425 unsigned Op0 = getRegForValue(I->getOperand(0)); in selectBinaryOp() local
426 if (!Op0) // Unhandled operand. Halt "fast" selection and bail. in selectBinaryOp()
448 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, in selectBinaryOp()
461 ISDOpcode, Op0, Op0IsKill, CF); in selectBinaryOp()
476 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill); in selectBinaryOp()
1298 unsigned Op0 = getRegForValue(I->getOperand(0)); in selectBitCast() local
1299 if (!Op0) // Unhandled operand. Halt "fast" selection and bail. in selectBitCast()
1312 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0); in selectBitCast()
1318 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); in selectBitCast()
1534 const Value *Op0 = EVI->getOperand(0); in selectExtractValue() local
1535 Type *AggTy = Op0->getType(); in selectExtractValue()
1539 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0); in selectExtractValue()
1542 else if (isa<Instruction>(Op0)) in selectExtractValue()
1543 ResultReg = FuncInfo.InitializeRegForValue(Op0); in selectExtractValue()
1742 unsigned FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, in fastEmit_ri_() argument
1761 unsigned ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm); in fastEmit_ri_()
1782 return fastEmit_rr(VT, VT, Opcode, Op0, Op0IsKill, MaterialReg, IsImmKill); in fastEmit_ri_()
1816 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_r() argument
1821 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
1825 .addReg(Op0, getKillRegState(Op0IsKill)); in fastEmitInst_r()
1828 .addReg(Op0, getKillRegState(Op0IsKill)); in fastEmitInst_r()
1837 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rr() argument
1843 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1848 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr()
1852 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr()
1861 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rrr() argument
1868 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
1874 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rrr()
1879 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rrr()
1889 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_ri() argument
1894 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
1898 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_ri()
1902 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_ri()
1911 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rii() argument
1917 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
1921 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rii()
1926 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rii()
1955 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rri() argument
1961 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
1966 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rri()
1971 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rri()
1996 unsigned FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, in fastEmitInst_extractsubreg() argument
1999 assert(TargetRegisterInfo::isVirtualRegister(Op0) && in fastEmitInst_extractsubreg()
2001 const TargetRegisterClass *RC = MRI.getRegClass(Op0); in fastEmitInst_extractsubreg()
2002 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx)); in fastEmitInst_extractsubreg()
2004 ResultReg).addReg(Op0, getKillRegState(Op0IsKill), Idx); in fastEmitInst_extractsubreg()
2010 unsigned FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) { in fastEmitZExtFromI1() argument
2011 return fastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1); in fastEmitZExtFromI1()