71                            const DebugLoc &DL, unsigned Reg, unsigned Lane,
77                                  unsigned Lane, const TargetRegisterClass *TRC);
91                                 unsigned Lane, unsigned ToInsert);
429                                        unsigned Lane, bool QPR) {  in createDupLane()  argument
438                    .addImm(Lane));  in createDupLane()
446     const DebugLoc &DL, unsigned DReg, unsigned Lane,  in createExtractSubreg()  argument
453     .addReg(DReg, 0, Lane);  in createExtractSubreg()
493     const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) {  in createInsertSubreg()  argument
501     .addImm(Lane);  in createInsertSubreg()
558     unsigned Lane;  in optimizeAllLanesPattern()  local
560       case ARM::ssub_0: Lane = 0; break;  in optimizeAllLanesPattern()
561       case ARM::ssub_1: Lane = 1; break;  in optimizeAllLanesPattern()
571     Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);  in optimizeAllLanesPattern()