219       bool operator== (RegisterRef RR) const {  in operator ==()
220         return Reg == RR.Reg && Sub == RR.Sub;  in operator ==()
222       bool operator!= (RegisterRef RR) const { return !operator==(RR); }  in operator !=()
223       bool operator< (RegisterRef RR) const {  in operator <()
224         return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);  in operator <()
236     void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
272     bool isIntReg(RegisterRef RR, unsigned &BW);
323 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,  in addRefToMap()  argument
325   unsigned Mask = getMaskForSub(RR.Sub) | Exec;  in addRefToMap()
326   ReferenceMap::iterator F = Map.find(RR.Reg);  in addRefToMap()
328     Map.insert(std::make_pair(RR.Reg, Mask));  in addRefToMap()
334 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,  in isRefInMap()  argument
336   ReferenceMap::iterator F = Map.find(RR.Reg);  in isRefInMap()
339   unsigned Mask = getMaskForSub(RR.Sub) | Exec;  in isRefInMap()
765       RegisterRef RR = Op;  in getReachingDefForPred()  local
766       if (RR.Reg == PredR) {  in getReachingDefForPred()
770       if (RR.Reg != RD.Reg)  in getReachingDefForPred()
775       if (RR.Sub == RD.Sub)  in getReachingDefForPred()
777       if (RR.Sub == 0 || RD.Sub == 0)  in getReachingDefForPred()
800     RegisterRef RR = Op;  in canMoveOver()  local
804     if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))  in canMoveOver()
807     if (isRefInMap(RR, Defs, Exec_Then))  in canMoveOver()
810     if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then))  in canMoveOver()
1011       RegisterRef RR = Op;  in predicate()  local
1012       if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))  in predicate()
1016       addRefToMap(RR, Map, Exec);  in predicate()
1098 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {  in isIntReg()  argument
1099   if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))  in isIntReg()
1101   const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);  in isIntReg()
1107     BW = (RR.Sub != 0) ? 32 : 64;  in isIntReg()