Lines Matching refs:OpNo
269 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, in getBranchTargetOpValue() argument
273 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValue()
292 getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo, in getBranchTargetOpValue1SImm16() argument
296 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValue1SImm16()
315 getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo, in getBranchTargetOpValueMMR6() argument
319 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValueMMR6()
339 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, in getBranchTarget7OpValueMM() argument
343 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTarget7OpValueMM()
361 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, in getBranchTargetOpValueMMPC10() argument
365 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValueMMPC10()
383 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, in getBranchTargetOpValueMM() argument
387 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValueMM()
406 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, in getBranchTarget21OpValue() argument
410 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTarget21OpValue()
429 getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo, in getBranchTarget21OpValueMM() argument
433 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTarget21OpValueMM()
452 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo, in getBranchTarget26OpValue() argument
456 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTarget26OpValue()
475 const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, in getBranchTarget26OpValueMM() argument
478 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTarget26OpValueMM()
498 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo, in getJumpOffset16OpValue() argument
502 const MCOperand &MO = MI.getOperand(OpNo); in getJumpOffset16OpValue()
517 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, in getJumpTargetOpValue() argument
521 const MCOperand &MO = MI.getOperand(OpNo); in getJumpTargetOpValue()
535 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, in getJumpTargetOpValueMM() argument
539 const MCOperand &MO = MI.getOperand(OpNo); in getJumpTargetOpValueMM()
553 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, in getUImm5Lsl2Encoding() argument
557 const MCOperand &MO = MI.getOperand(OpNo); in getUImm5Lsl2Encoding()
572 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, in getSImm3Lsa2Value() argument
576 const MCOperand &MO = MI.getOperand(OpNo); in getSImm3Lsa2Value()
586 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, in getUImm6Lsl2Encoding() argument
590 const MCOperand &MO = MI.getOperand(OpNo); in getUImm6Lsl2Encoding()
600 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, in getSImm9AddiuspValue() argument
604 const MCOperand &MO = MI.getOperand(OpNo); in getSImm9AddiuspValue()
781 unsigned MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo, in getMemEncoding() argument
785 assert(MI.getOperand(OpNo).isReg()); in getMemEncoding()
786 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16; in getMemEncoding()
787 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncoding()
796 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo, in getMemEncodingMMImm4() argument
800 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4()
801 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), in getMemEncodingMMImm4()
803 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), in getMemEncodingMMImm4()
810 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo, in getMemEncodingMMImm4Lsl1() argument
814 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4Lsl1()
815 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), in getMemEncodingMMImm4Lsl1()
817 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), in getMemEncodingMMImm4Lsl1()
824 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, in getMemEncodingMMImm4Lsl2() argument
828 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4Lsl2()
829 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), in getMemEncodingMMImm4Lsl2()
831 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), in getMemEncodingMMImm4Lsl2()
838 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, in getMemEncodingMMSPImm5Lsl2() argument
842 assert(MI.getOperand(OpNo).isReg() && in getMemEncodingMMSPImm5Lsl2()
843 (MI.getOperand(OpNo).getReg() == Mips::SP || in getMemEncodingMMSPImm5Lsl2()
844 MI.getOperand(OpNo).getReg() == Mips::SP_64) && in getMemEncodingMMSPImm5Lsl2()
846 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), in getMemEncodingMMSPImm5Lsl2()
853 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, in getMemEncodingMMGPImm7Lsl2() argument
857 assert(MI.getOperand(OpNo).isReg() && in getMemEncodingMMGPImm7Lsl2()
858 MI.getOperand(OpNo).getReg() == Mips::GP && in getMemEncodingMMGPImm7Lsl2()
861 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), in getMemEncodingMMGPImm7Lsl2()
868 getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo, in getMemEncodingMMImm9() argument
872 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm9()
873 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, in getMemEncodingMMImm9()
875 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI); in getMemEncodingMMImm9()
881 getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo, in getMemEncodingMMImm11() argument
885 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm11()
886 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, in getMemEncodingMMImm11()
888 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncodingMMImm11()
894 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, in getMemEncodingMMImm12() argument
904 OpNo = MI.getNumOperands() - 2; in getMemEncodingMMImm12()
909 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm12()
910 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16; in getMemEncodingMMImm12()
911 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncodingMMImm12()
917 getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo, in getMemEncodingMMImm16() argument
921 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm16()
922 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, in getMemEncodingMMImm16()
924 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncodingMMImm16()
930 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, in getMemEncodingMMImm4sp() argument
942 OpNo = MI.getNumOperands() - 2; in getMemEncodingMMImm4sp()
947 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4sp()
949 assert(MI.getOperand(OpNo+1).isImm()); in getMemEncodingMMImm4sp()
950 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncodingMMImm4sp()
958 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo, in getSizeInsEncoding() argument
961 assert(MI.getOperand(OpNo-1).isImm()); in getSizeInsEncoding()
962 assert(MI.getOperand(OpNo).isImm()); in getSizeInsEncoding()
963 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI); in getSizeInsEncoding()
964 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); in getSizeInsEncoding()
971 MipsMCCodeEmitter::getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo, in getUImmWithOffsetEncoding() argument
974 assert(MI.getOperand(OpNo).isImm()); in getUImmWithOffsetEncoding()
975 unsigned Value = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); in getUImmWithOffsetEncoding()
981 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, in getSimm19Lsl2Encoding() argument
984 const MCOperand &MO = MI.getOperand(OpNo); in getSimm19Lsl2Encoding()
1003 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, in getSimm18Lsl3Encoding() argument
1006 const MCOperand &MO = MI.getOperand(OpNo); in getSimm18Lsl3Encoding()
1009 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); in getSimm18Lsl3Encoding()
1025 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, in getUImm3Mod8Encoding() argument
1028 assert(MI.getOperand(OpNo).isImm()); in getUImm3Mod8Encoding()
1029 const MCOperand &MO = MI.getOperand(OpNo); in getUImm3Mod8Encoding()
1034 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo, in getUImm4AndValue() argument
1037 assert(MI.getOperand(OpNo).isImm()); in getUImm4AndValue()
1038 const MCOperand &MO = MI.getOperand(OpNo); in getUImm4AndValue()
1062 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo, in getRegisterListOpValue() argument
1070 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) { in getRegisterListOpValue()
1082 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, in getRegisterListOpValue16() argument
1089 MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo, in getRegisterPairOpValue() argument
1092 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); in getRegisterPairOpValue()
1096 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo, in getMovePRegPairOpValue() argument
1130 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, in getSimm23Lsl2Encoding() argument
1133 const MCOperand &MO = MI.getOperand(OpNo); in getSimm23Lsl2Encoding()