Lines Matching refs:VA
232 CCValAssign &VA = RVLocs[i]; in LowerReturn_32() local
233 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
237 if (VA.needsCustom()) { in LowerReturn_32()
238 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
249 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag); in LowerReturn_32()
251 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
252 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn_32()
253 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
256 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); in LowerReturn_32()
260 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
315 CCValAssign &VA = RVLocs[i]; in LowerReturn_64() local
316 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_64()
320 switch (VA.getLocInfo()) { in LowerReturn_64()
323 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
326 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
329 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
337 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { in LowerReturn_64()
343 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
351 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn_64()
355 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
400 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments_32() local
415 if (VA.isRegLoc()) { in LowerFormalArguments_32()
416 if (VA.needsCustom()) { in LowerFormalArguments_32()
417 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerFormalArguments_32()
420 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
445 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue); in LowerFormalArguments_32()
450 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments_32()
452 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments_32()
454 else if (VA.getLocVT() != MVT::i32) { in LowerFormalArguments_32()
456 DAG.getValueType(VA.getLocVT())); in LowerFormalArguments_32()
457 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); in LowerFormalArguments_32()
463 assert(VA.isMemLoc()); in LowerFormalArguments_32()
465 unsigned Offset = VA.getLocMemOffset()+StackOffset; in LowerFormalArguments_32()
468 if (VA.needsCustom()) { in LowerFormalArguments_32()
469 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32); in LowerFormalArguments_32()
476 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, in LowerFormalArguments_32()
504 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue); in LowerFormalArguments_32()
514 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { in LowerFormalArguments_32()
515 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, in LowerFormalArguments_32()
518 } else if (VA.getValVT() == MVT::f128) { in LowerFormalArguments_32()
601 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments_64() local
602 if (VA.isRegLoc()) { in LowerFormalArguments_64()
607 unsigned VReg = MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_64()
608 getRegClassFor(VA.getLocVT())); in LowerFormalArguments_64()
609 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); in LowerFormalArguments_64()
612 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) in LowerFormalArguments_64()
613 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
618 switch (VA.getLocInfo()) { in LowerFormalArguments_64()
620 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
621 DAG.getValueType(VA.getValVT())); in LowerFormalArguments_64()
624 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
625 DAG.getValueType(VA.getValVT())); in LowerFormalArguments_64()
632 if (VA.isExtInLoc()) in LowerFormalArguments_64()
633 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); in LowerFormalArguments_64()
640 assert(VA.isMemLoc()); in LowerFormalArguments_64()
643 unsigned Offset = VA.getLocMemOffset() + ArgArea; in LowerFormalArguments_64()
644 unsigned ValSize = VA.getValVT().getSizeInBits() / 8; in LowerFormalArguments_64()
648 if (VA.isExtInLoc()) in LowerFormalArguments_64()
652 VA.getValVT(), DL, Chain, in LowerFormalArguments_64()
795 CCValAssign &VA = ArgLocs[i]; in LowerCall_32() local
809 switch (VA.getLocInfo()) { in LowerCall_32()
813 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
816 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
819 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
822 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall_32()
827 assert(VA.needsCustom()); in LowerCall_32()
839 if (VA.needsCustom()) { in LowerCall_32()
840 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerCall_32()
842 if (VA.isMemLoc()) { in LowerCall_32()
843 unsigned Offset = VA.getLocMemOffset() + StackOffset; in LowerCall_32()
856 if (VA.getLocVT() == MVT::f64) { in LowerCall_32()
874 if (VA.isRegLoc()) { in LowerCall_32()
875 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Part0)); in LowerCall_32()
891 unsigned Offset = VA.getLocMemOffset() + StackOffset; in LowerCall_32()
911 if (VA.isRegLoc()) { in LowerCall_32()
912 if (VA.getLocVT() != MVT::f32) { in LowerCall_32()
913 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32()
917 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32()
921 assert(VA.isMemLoc()); in LowerCall_32()
925 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + StackOffset, in LowerCall_32()
1105 const CCValAssign &VA = ArgLocs[i]; in fixupVariableFloatArgs() local
1106 MVT ValTy = VA.getLocVT(); in fixupVariableFloatArgs()
1109 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) in fixupVariableFloatArgs()
1112 if (Outs[VA.getValNo()].IsFixed) in fixupVariableFloatArgs()
1121 unsigned Offset = argSize * (VA.getLocReg() - firstReg); in fixupVariableFloatArgs()
1129 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(), in fixupVariableFloatArgs()
1135 NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(), in fixupVariableFloatArgs()
1140 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(), in fixupVariableFloatArgs()
1141 Offset, VA.getLocVT(), VA.getLocInfo()); in fixupVariableFloatArgs()
1195 const CCValAssign &VA = ArgLocs[i]; in LowerCall_64() local
1199 switch (VA.getLocInfo()) { in LowerCall_64()
1205 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1208 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1211 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1216 if (!VA.needsCustom() || VA.getValVT() != MVT::f128 in LowerCall_64()
1217 || VA.getLocVT() != MVT::i128) in LowerCall_64()
1218 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerCall_64()
1222 if (VA.isRegLoc()) { in LowerCall_64()
1223 if (VA.needsCustom() && VA.getValVT() == MVT::f128 in LowerCall_64()
1224 && VA.getLocVT() == MVT::i128) { in LowerCall_64()
1226 unsigned Offset = 8 * (VA.getLocReg() - SP::I0); in LowerCall_64()
1245 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), in LowerCall_64()
1247 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1), in LowerCall_64()
1254 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { in LowerCall_64()
1261 ArgLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerCall_64()
1269 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg)); in LowerCall_64()
1273 assert(VA.isMemLoc()); in LowerCall_64()
1279 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + in LowerCall_64()
1363 CCValAssign &VA = RVLocs[i]; in LowerCall_64() local
1364 unsigned Reg = toCallerWindow(VA.getLocReg()); in LowerCall_64()
1382 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) in LowerCall_64()
1383 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, in LowerCall_64()
1388 switch (VA.getLocInfo()) { in LowerCall_64()
1390 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall_64()
1391 DAG.getValueType(VA.getValVT())); in LowerCall_64()
1394 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall_64()
1395 DAG.getValueType(VA.getValVT())); in LowerCall_64()
1402 if (VA.isExtInLoc()) in LowerCall_64()
1403 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV); in LowerCall_64()