Lines Matching refs:AX

57 // AL is really implied by AX, but the registers in Defs must match the
60 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
67 // AX,DX = AX*GR16
68 let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
85 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
93 // AX,DX = AX*[mem16]
95 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
112 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
115 // AX,DX = AX*GR16
116 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
130 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
133 // AX,DX = AX*[mem16]
134 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
297 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
298 def DIV8r  : I<0xF6, MRM6r, (outs),  (ins GR8:$src),    // AX/r8 = AL,AH
300 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
301 def DIV16r : I<0xF7, MRM6r, (outs),  (ins GR16:$src),   // DX:AX/r16 = AX,DX
313 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
314 def DIV8m  : I<0xF6, MRM6m, (outs), (ins i8mem:$src),   // AX/[mem8] = AL,AH
317 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
318 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src),  // DX:AX/[mem16] = AX,DX
334 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
335 def IDIV8r : I<0xF6, MRM7r, (outs),  (ins GR8:$src),    // AX/r8 = AL,AH
337 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
338 def IDIV16r: I<0xF7, MRM7r, (outs),  (ins GR16:$src),   // DX:AX/r16 = AX,DX
350 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
351 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src),   // AX/[mem8] = AL,AH
354 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
355 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src),  // DX:AX/[mem16] = AX,DX
1021   def NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
1104   def NAME#16i16 : BinOpAI_RFF<BaseOpc4, mnemonic, Xi16, AX,
1182   def NAME#16i16 : BinOpAI_F<BaseOpc4, mnemonic, Xi16, AX,
1258   def TEST16i16  : BinOpAI_F<0xA8, "test", Xi16, AX,