566    surf_level->dcc_offset = 0;  in gfx6_compute_level()
581          surf_level->dcc_offset = surf->dcc_size;  in gfx6_compute_level()
583          surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;  in gfx6_compute_level()
2111    surf->dcc_offset = surf->display_dcc_offset = 0;  in ac_compute_surface()
2150       surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment);  in ac_compute_surface()
2151       surf->total_size = surf->dcc_offset + surf->dcc_size;  in ac_compute_surface()
2161    surf->dcc_offset = 0;  in ac_surface_zero_dcc_fields()
2265       uint64_t dcc_offset = 0;  in ac_surface_get_bo_metadata()  local
2267       if (surf->dcc_offset) {  in ac_surface_get_bo_metadata()
2268          dcc_offset = surf->display_dcc_offset ? surf->display_dcc_offset : surf->dcc_offset;  in ac_surface_get_bo_metadata()
2269          assert((dcc_offset >> 8) != 0 && (dcc_offset >> 8) < (1 << 24));  in ac_surface_get_bo_metadata()
2273       *tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, dcc_offset >> 8);  in ac_surface_get_bo_metadata()
2365          surf->dcc_offset = (uint64_t)desc[7] << 8;  in ac_surface_set_umd_metadata()
2369          surf->dcc_offset =  in ac_surface_set_umd_metadata()
2381          surf->dcc_offset =  in ac_surface_set_umd_metadata()
2413       desc[7] = surf->dcc_offset >> 8;  in ac_surface_get_umd_metadata()
2416       desc[7] = surf->dcc_offset >> 8;  in ac_surface_get_umd_metadata()
2418       desc[5] |= S_008F24_META_DATA_ADDRESS(surf->dcc_offset >> 40);  in ac_surface_get_umd_metadata()
2423       desc[6] |= S_00A018_META_DATA_ADDRESS_LO(surf->dcc_offset >> 8);  in ac_surface_get_umd_metadata()
2424       desc[7] = surf->dcc_offset >> 16;  in ac_surface_get_umd_metadata()
2490    if (surf->dcc_offset)  in ac_surface_override_offset_stride()
2491       surf->dcc_offset += offset;  in ac_surface_override_offset_stride()