Lines Matching defs:bits
264 {"bits": [0, 20], "name": "BYTE_COUNT"}, array
265 {"bits": [21, 21], "name": "DISABLE_WR_CONFIRM"}, array
266 {"bits": [22, 23], "enum_ref": "COMMAND__SRC_SWAP", "name": "SRC_SWAP"}, array
267 {"bits": [24, 25], "enum_ref": "COMMAND__SRC_SWAP", "name": "DST_SWAP"}, array
268 {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"}, array
269 {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"}, array
270 {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"}, array
271 {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"}, array
272 {"bits": [30, 30], "name": "RAW_WAIT"} array
277 {"bits": [0, 25], "name": "BYTE_COUNT"}, array
278 {"bits": [26, 26], "enum_ref": "COMMAND__SAS", "name": "SAS"}, array
279 {"bits": [27, 27], "enum_ref": "COMMAND__SAS", "name": "DAS"}, array
280 {"bits": [28, 28], "enum_ref": "COMMAND__SAIC", "name": "SAIC"}, array
281 {"bits": [29, 29], "enum_ref": "COMMAND__SAIC", "name": "DAIC"}, array
282 {"bits": [30, 30], "name": "RAW_WAIT"}, array
283 {"bits": [31, 31], "name": "DISABLE_WR_CONFIRM"} array
288 {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL", "name": "DST_SEL"}, array
289 {"bits": [16, 16], "name": "WR_ONE_ADDR"}, array
290 {"bits": [20, 20], "name": "WR_CONFIRM"}, array
291 {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"} array
296 {"bits": [8, 11], "enum_ref": "CONTROL__DST_SEL_cik", "name": "DST_SEL"}, array
297 {"bits": [16, 16], "name": "WR_ONE_ADDR"}, array
298 {"bits": [20, 20], "name": "WR_CONFIRM"}, array
299 {"bits": [30, 31], "enum_ref": "CONTROL__ENGINE_SEL", "name": "ENGINE_SEL"} array
304 {"bits": [0, 31], "name": "SRC_ADDR_LO"} array
309 {"bits": [0, 15], "name": "SRC_ADDR_HI"}, array
310 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"}, array
311 {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, array
312 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"}, array
313 {"bits": [31, 31], "name": "CP_SYNC"} array
318 {"bits": [0, 15], "name": "SRC_ADDR_HI"}, array
319 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"}, array
320 {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, array
321 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"}, array
322 {"bits": [31, 31], "name": "CP_SYNC"} array
327 {"bits": [0, 15], "name": "SRC_ADDR_HI"}, array
328 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"}, array
329 {"bits": [27, 27], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, array
330 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"}, array
331 {"bits": [31, 31], "name": "CP_SYNC"} array
336 {"bits": [0, 31], "name": "DST_ADDR_LO"} array
341 {"bits": [0, 15], "name": "DST_ADDR_HI"} array
346 {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, array
347 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL", "name": "DST_SEL"}, array
348 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL", "name": "SRC_SEL"}, array
349 {"bits": [31, 31], "name": "CP_SYNC"} array
354 {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, array
355 {"bits": [13, 14], "name": "SRC_CACHE_POLICY"}, array
356 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_cik", "name": "DST_SEL"}, array
357 {"bits": [25, 26], "name": "DST_CACHE_POLICY"}, array
358 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"}, array
359 {"bits": [31, 31], "name": "CP_SYNC"} array
364 {"bits": [0, 0], "enum_ref": "CP_DMA_WORD1__ENGINE", "name": "ENGINE"}, array
365 {"bits": [13, 14], "name": "SRC_CACHE_POLICY"}, array
366 {"bits": [20, 21], "enum_ref": "CP_DMA_WORD1__DST_SEL_gfx9", "name": "DST_SEL"}, array
367 {"bits": [25, 26], "name": "DST_CACHE_POLICY"}, array
368 {"bits": [29, 30], "enum_ref": "CP_DMA_WORD1__SRC_SEL_cik", "name": "SRC_SEL"}, array
369 {"bits": [31, 31], "name": "CP_SYNC"} array
374 {"bits": [0, 1], "enum_ref": "GCR_GLI_INV", "name": "GLI_INV"}, array
375 {"bits": [2, 3], "enum_ref": "GCR_GL1_RANGE", "name": "GL1_RANGE"}, array
376 {"bits": [4, 4], "name": "GLM_WB"}, array
377 {"bits": [5, 5], "name": "GLM_INV"}, array
378 {"bits": [6, 6], "name": "GLK_WB"}, array
379 {"bits": [7, 7], "name": "GLK_INV"}, array
380 {"bits": [8, 8], "name": "GLV_INV"}, array
381 {"bits": [9, 9], "name": "GL1_INV"}, array
382 {"bits": [10, 10], "name": "GL2_US"}, array
383 {"bits": [11, 12], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"}, array
384 {"bits": [13, 13], "name": "GL2_DISCARD"}, array
385 {"bits": [14, 14], "name": "GL2_INV"}, array
386 {"bits": [15, 15], "name": "GL2_WB"}, array
387 {"bits": [16, 17], "enum_ref": "GCR_SEQ", "name": "SEQ"}, array
388 {"bits": [18, 18], "name": "RANGE_IS_PA"} array
393 {"bits": [0, 19], "name": "IB_SIZE"}, array
394 {"bits": [20, 20], "name": "CHAIN"}, array
395 {"bits": [23, 23], "name": "VALID"} array
400 {"bits": [0, 5], "name": "EVENT_TYPE"}, array
401 {"bits": [8, 11], "name": "EVENT_INDEX"}, array
402 {"bits": [12, 12], "name": "GLM_WB"}, array
403 {"bits": [13, 13], "name": "GLM_INV"}, array
404 {"bits": [14, 14], "name": "GLV_INV"}, array
405 {"bits": [15, 15], "name": "GL1_INV"}, array
406 {"bits": [16, 16], "name": "GL2_US"}, array
407 {"bits": [17, 18], "enum_ref": "GCR_GL2_RANGE", "name": "GL2_RANGE"}, array
408 {"bits": [19, 19], "name": "GL2_DISCARD"}, array
409 {"bits": [20, 20], "name": "GL2_INV"}, array
410 {"bits": [21, 21], "name": "GL2_WB"}, array
411 {"bits": [22, 23], "enum_ref": "GCR_SEQ", "name": "SEQ"} array